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Table 2-6
NMG2090 Pin Descriptions (continued)
Pin Name
PCI Interface (continued)
C/BE3#
C/BE2
C/BE1
C/BE0
FRAME#
PAR
IRDY#
TRDY#
STOP#
DEVSEL#
IDSEL
BCLK
RESET#
INTA#
Type
Pin No.
I
63
51
40
31
I
72
I/O
65
I
73
O
67
S/T/S
O
68
S/T/S
O
69
S/T/S
I
81
I
71
I
84
O
70
O/D
Multiplexed Command and Byte Enable These
multiplexed pins provide the command during address phase
and byte enable(s) during data phase to the NMG2
Frame This active-low signal is driven by the bus master to
indicate the beginning and duration of an access.
Parity Even parity across AD31 :0 & C/BE3:0# is driven by
the bus master during address and write data phases and
driven by NM2090during read data phases
Initiator Ready This active low signal indicates the bus
master's ability to complete the current data phase of the
transaction. During a write cycle, IDRY# indicates that valid
data is present on AD31 :00 during a read cycle it indicates
the master is prepared to accept data. Wait states will be
inserted until both IRDY# and TRDY# are asserted together.
Target Ready This active low signal indicates NMG2's ability
to complete the current data phase of the transaction. During
a read cycle TRDY# indicates that valid data is present on
AD 31:00. During a write, it indicates NM2090is prepared to
accept data. Wait states will be inserted until both TRDY# &
IRDY# are asserted together.
Stop This active low signal indicates that NM2090is
requesting the master to terminate at the end of current
transaction
Device Select This active low signal indicates that
NM2090has decoded its address as the target of the current
access.
Initialization Device Select This is selected during
configuration read and write transactions.
Bus Clock This input provides the timing for all transactions
on PCL bus.
Reset This active-low input is used to initialize NMG2.
Interrupt request A This active low "level sensitive" output
indicates an interrupt request.
Descriptions
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