Cl-Pd6730 Pin Descriptions - Acer AcerNote 970 Service Manual

The following table lists the pin descriptions
Table 2-14

CL-PD6730 Pin Descriptions

Pin Name
PCI Bus Interface Pins
AD[31:0] PCI Bus Address Input / Data Input/Output:
These pins connect to PCI bus signals AD[31:0].
C/BE[3:0]# PCI Bus Command / Byte Enable: The
command signaling and byte enables are
multiplexed on the same pins. During the address
phase of a transaction, C/BE[3:0]# are interpreted
as the bus commands. During the data phase,
C/BE[3:0]# are interpreted as byte enables. The
byte enables are to be valid for the entirety of each
data phase, and they indicate which bytes in the
32-bit data path are to carry meaningful data for
the current data phase.
FRAME# Cycle Frame: This input indicates to the CL-
PD6730 that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue.
When FRAME# is deasserted, the transaction is in
its final phase.
IRDY# Initiator Ready: This input indicates the initiating
agent's ability to complete the current data phase
of the transaction. IRDY# is used in conjunction
with TRDY#.
TRDY# Target Ready: This output indicates the CL-
PD6730's ability to complete the current data
STOP# Stop: This output indicates the current target is
requesting the master to stop the current
transaction.
IDSEL Initialization Device Select: This input is used as
a chip select during configuration read and write
transactions. This is a point-to-point signal. The
CL-PD6730 must be connected to its own unique
IDSEL line (from the PCI bus arbiter or one of the
high-order AD bus pins).
DEVSEL# Device Select: The CL-PD6730 drives this output
active (low) when it has decoded the PCI dress PC
as one that it is programmed to support, thereby
acting as the target for the current PCI cycle.
Description Pin Number I/O
4, 5, 7-12, 16-20, I/O
22-24, 48 49, 51-
56
13, 25, 36, 47
27 I
29 I
30 O-TS
32 O-TS
15
31 O-TS
Power
4
4
4
4