General-Purpose Input/Output (Gpio) - Texas Instruments TMS320C6455 Manual

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7.21 General-Purpose Input/Output (GPIO)

7.21.1 GPIO Device-Specific Information
On the C6455 device, the GPIO peripheral pins GP[15:8] and GP[3:0] are muxed with the UTOPIA, PCI,
and McBSP1 peripheral pins and the SYSCLK4 signal. For more detailed information on device/peripheral
configuration and the C6455 device pin muxing, see
7.21.2 GPIO Peripheral Register Descriptions
HEX ADDRESS RANGE
02B0 0008
02B0 000C
02B0 0010
02B0 0014
02B0 0018
02B0 001C
02B0 0020
02B0 0024
02B0 0028
02B0 002C
02B0 0030
02B0 008C
02B0 0090 - 02B0 00FF
02B0 0100 - 02B0 3FFF
Copyright © 2005–2012, Texas Instruments Incorporated
Section
Table 7-113. GPIO Registers
ACRONYM
BINTEN GPIO interrupt per bank enable register
- Reserved
DIR GPIO Direction Register
OUT_DATA GPIO Output Data register
SET_DATA GPIO Set Data register
CLR_DATA GPIO Clear Data Register
IN_DATA GPIO Input Data Register
SET_RIS_TRIG GPIO Set Rising Edge Interrupt Register
CLR_RIS_TRIG GPIO Clear Rising Edge Interrupt Register
SET_FAL_TRIG GPIO Set Falling Edge Interrupt Register
CLR_FAL_TRIG GPIO Clear Falling Edge Interrupt Register
- Reserved
- Reserved
- Reserved
C64x+ Peripheral Information and Electrical Specifications
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Product Folder Link(s): TMS320C6455
SPRS276M – MAY 2005 – REVISED MARCH 2012
3, Device Configuration.
REGISTER NAME
TMS320C6455
245