Timing Analysis - Intel 440GX Design Manual

2.7

Timing Analysis

To determine the available flight time window perform an initial timing analysis. Analysis of setup
and hold conditions will determine the minimum and maximum flight time bounds for the host bus.
Use the following equations to establish the system flight time limits.
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Table 2-7. Intel Pentium
Driver
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Pentium
processor
AGPset
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Pentium
processor
The terms used in the equations are described in
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Table 2-8. Intel Pentium
Term
T
cycle
T
flight,min
T
flight,max
T
co,max
T
co,min
T
su
T
h
T
skew,CLK
T
skew,PCB
T
jit
T
adj
T
clk,min
T
clk,max
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Intel 440GX AGPset Design Guide
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II Processor and Inte
Receiver
II
T
AGPset
flight ,min
T
flight ,max
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Pentium
II
T
processor
flight ,min
T
flight ,max
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II Pentium II
T
flight ,min
processor
T
,max
flight
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II Processor and Intel
System cycle time. Defined as the reciprocal of the frequency
Minimum system flight time. Flight time is defined in
page 4-1.
Maximum system flight time. Flight time is defined in
page 4-1.
Maximum driver delay from input clock to output data.
Minimum driver delay from input clock to output data.
Minimum setup time. Defined as the time for which the input data must be valid prior to the input
clock.
Minimum hold time. Defined as the time for which the input data must remain valid after the input
clock.
Clock generator skew. Defined as the maximum delay variation between output clock signals
from the system clock generator.
PCB skew. Defined as the maximum delay variation between clock signals due to system board
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variation and Intel 440GX AGPset loading variation.
Clock jitter. Defined as the maximum edge to edge variation in a given clock signal.
Multi-bit timing adjustment factor. This term accounts for the additional delay that occurs in the
network when multiple data bits switch in the same cycle. The adjustment factor includes such
mechanisms as package and PCB crosstalk, high inductance current return paths, and
simultaneous switching noise.
Minimum clock substrate delay. Defined as the minimum adjustment factor that accounts for the
delay of the clock trace on the Pentium II processor substrate.
Minimum clock substrate delay. Defined as the maximum adjustment factor that accounts for the
delay of the clock trace on the Pentium II processor substrate.
Motherboard Layout and Routing Guidelines
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l 440GX AGPset System Timing Equations
Equation
T T T
co
hold ,min skew CLK ,
T T T T
cycle co ,max su skew CLK ,
T T T
hold co ,min skew CLK ,
T T T T
cycle co ,max su skew CLK ,
T T T
hold co ,min skew CLK ,
T T T T
,max
cycle co su skew CLK
Table 2-8.
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440GX AGPset System Timing Terms
Description
Section 4, "Debug Recommendations" on
Section 4, "Debug Recommendations" on
T T
skew PCB , clk ,max
T T T T
skew PCB , jit adj clk
T T
skew PCB , clk ,min
T T T
skew PCB , jit adj
T
skew PCB ,
T T T
, ,
skew PCB jit adj
,min
T
clk ,max
2-17