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3.7.3
PIIX4E Power And Ground Pins
•
Vcc, Vcc(RTC), Vcc(SUS), and Vcc(USB) must be tied to 3.3V.
•
V
REF
simultaneous to Vcc, and it must be power down after or simultaneous to Vcc. For the layout
guidelines, refer to the Pin Description section of the PIIX4E datasheet. The V
can be shared between 82443GX and the PIIX4E. If the circuitry is placed close to the PIIX4E,
then ensure that an extra 1uF capacitor is placed on the V
— STR support: For systems implementing STR support, a separate V
used for each of the two devices since the PIIX4E Core and the 82443GX Host Bridge
should be supplied by the different power planes.
— No STR support: The V
the circuitry is placed close to the PIIX4E, then ensure that an extra 1uF capacitor is
placed on the V
•
Use a Schottky diode in the V
because there is an internal diode in parallel to the Schottky diode that does not have high
current capability. The Schottky diode will begin to conduct first, therefore carrying the high
current.
•
V
REF
•
Tie Vss and Vss(USB) to ground.
Table 3-9. PIIX4E PWR & GND
VCC
E9
E11
E12
E16
F5
F6
F14
3.8
PCI Bus Signals
A specific board sensitivity has been identified that may result in a low going glitch on a deasserted
PCIRST# signal when it is lightly loaded. This glitch may occur as a result of VCC droop caused
by simultaneous switching of most/all AD[31:0] signals from 0 to 1. This glitch can in some
designs be low enough (below 1.7V) to interfere with proper operation of the Host PCI Bridge
Controller component.
This sensitivity manifests itself on designs where PCIRST# is lightly loaded with less than
approximately 50pF, or is not driving the entire PCI bus. Design features that could aggravate the
problem are; an in-line active component on the PCIRST# signal, such as an AND gate or, lack of a
series termination resistor on the PCIRST# signal at the PIIX4 or PIIX4E.
There are several improvements that can be implemented individually or in any combination. First,
a series termination resistor between 22 and 33 ohms placed close to the PIIX4/PIIX4E will help
reduce the glitch. Second, an external capacitor of approximately 47pF will help reduce the glitch.
®
Intel
440GX AGPset Design Guide
must be tied to 5V in a 5V tolerant system. This signal must be power up before or
REF
pin of the 82443GX.
REF
REF
can be tied to Vcc in a non-5V tolerant system.
VCC(RTC)
VCC(SUS)
F15
L16
N16
G6
R16
P15
R6
R7
R15
T6
REF
circuitry can be shared between 82443GX and the PIIX4E. If
circuit for a minimum voltage drop from VCC
VCC(USB)
K5
Design Checklist
circuitry
REF
pin of the 82443GX.
circuit must be
REF
to V
3.3
VSS(USB)
VSS
J5
D10
L9-L12
E7
M9-M12
E13
J9-J12
K9-K12
REF
3-22
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