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4.3.2.1
Debug Considerations
•
As technology drives better low power modes, the Vcc
Amps. This may cause a regulator to go out of regulation. Place pads for a load resistance on
the Vcc
•
After meeting the guidelines in the Intel
high frequency and bulk decoupling capacitance sites as will fit near the processor slot.
•
Intel recommends using industry standard Voltage Regulator Modules designed for the
processor. However, previous VRM modules may not support future processors for Slot 1
unless built to VRM 8.2 specifications..
4.3.3
Debug Layout
•
Pay close attention to the keep out zones for the Logic Analyzer Interface (LAI). These keep
out zones are required to ensure that the LAI can be installed within a system.
4.3.3.1
Design Considerations
•
Plan as much space as possible for the Intel
additional cooling or other requirements for early Intel
4.3.4
Debug Procedures
•
When using an ITP565 In-Target Probe for the processor a common error is that the boundary
scan chain order in the ITP565.INI input file is not correct. Check the file to ensure that the
scan chain connections on your motherboard match the order provided the tool in this file.
This file needs to change based on what components are in the boundary scan chain. In DP
systems, the processor with PREQ0# and PRDY0# is considered processor 0, even if it is not
the first one in the chain. Processor 0 should be placed in its proper place in the order.
•
TCK noise may limit ITP speed or cause functional problems. Observe this signal with an
oscilloscope. The TCK speed may be changed from 10MHz to 1250Hz using the keyword,
TCLK = "value", in the [Debug Port] section of the ITP565.INI file. See the ITP HELP menu
"Changing the TCLK Signal Frequency" for the valid values. If you are having difficulty
initializing the ITP562, try slowing TCK.
•
ITP macros are available for the Intel
number of macros are provided (e.g., utilities to read/write any PCI configuration register) a
macro display POST codes and stop on a specified code, macros to dump the 82443GX and
PIIX4E register sets as well as processor specific registers, etc.
•
TDO out of each processor should have a 150
have a 150 pull-up (IERR# might be asserted during the APIC/MP message generation if an
insufficient pull-up is used.).
•
Watch out for incorrect clock voltages. BCLK, TCK, and PICCLK are all Vcc
•
PICCLK must be driven even if APIC is not used. The APIC bus executes MP initialization
even in a uni-processor system.
•
APIC may be disabled in BIOS for initial debug by clearing bit 11 in the APIC base MSR
(1Bh).
•
Be sure boundary scan chains are properly reset using the TRST# pin of each device in the
debug port chain.
®
Intel
440GX AGPset Design Guide
regulator in the event the regulator cannot approach 0 Amps.
CORE
current demand could approach 0
CORE
®
®
II Processor Datasheet, add as many extra
Pentium
®
®
Pentium
II processor(s). This will allow for
®
Pentium
®
440GX AGPset to assist in debugging your system. A
pull-up. PICD0# and PICD1# should each
Debug Recommendations
®
II processor(s).
signals.
2.5
4-5
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