Tables
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
viii
Recommended Trace Lengths for Dual Processor Designs2.......................2-8
Ringback Guidelines at the Intel
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System Timing Equations ...........................................................................2-17
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System Timing Terms .................................................................................2-17
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Timing Specifications..................................................................................2-18
Slot Connectivity ...........................................................................................3-2
82443GX Connectivity ................................................................................3-10
Strapping Options .......................................................................................3-13
SDRAM Connectivity ..................................................................................3-14
PIIX4E Connectivity ....................................................................................3-16
PIIX4E PWR & GND...................................................................................3-22
Non-PIIX4E IDE..........................................................................................3-24
Slot 1 Connector ...........................................................................................5-1
Attach Sink Suppor .......................................................................................5-1
Clock Driver Vendors....................................................................................5-3
FET Switch Vendors .....................................................................................5-3
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Pentium
II Processor Edge Fingers ...2-16
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Intel
440GX AGPset Design Guide