Table of Contents
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®
Intel
80219 General Purpose PCI Processor
Summary Table of Changes
Specification Changes
Steppings
No.
Page
A-0
1
X
24
Specification Clarifications
Steppings
No.
Page
A-0
1
X
26
2
X
26
3
X
27
4
X
27
5
X
27
6
X
28
7
X
28
Documentation Changes
No.
Document Revision
10
Signal NC2 was renamed to P_BMI (AE23). New function added to signal P_BMI.
Status
®
The Intel
80219 general purpose PCI processor is compliant with the PCI Local Bus
NoFix
Specification, Revision 2.2 but it is not compliant with PCI Local Bus Specification,
Revision 2.3
Modifications to the Hot-Debug procedure are necessary for the Intel
NoFix
purpose PCI processor when flat memory mapping is not used (Virtual Address =
Physical Address)
Doc
BAR0 Configuration When Using the Messaging Unit (MU)
Doc
Reading Unpopulated SDRAM Memory Banks
Doc
32-bit Writes-to-Unaligned 64-bit Addresses, are Promoted to 64-bit Aligned Writes
Doc
In-order Delivery not guaranteed for data blocks described by a single DMA descriptor
Doc
Writing to reserved registers can cause unexpected behavior
Page
Status
None for this revision of this specification update.
Specification Changes
Specification Clarifications
Documentation Changes
®
80219 general
Specification Update
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