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3.
BAR0 Configuration When Using the Messaging Unit (MU)
Issue:
When the BAR0 is configured as a prefetchable register by default and a burst request crosses into
or through the range of offsets 40h to 4Ch (i.e., this includes the Circular Queues), the transaction
is signaled a Target Abort immediately on the PCI/PCI-X bus, which may be read as an NMI by the
host BIOS.
Status:
Doc. Do not configure the BAR0 as prefetchable when using BAR0 and the non-prefetchable MU
registers (i.e., range of offsets 40h to 4Ch). Configure the BAR0 as non-prefetchable, IABAR0[3],
when accessing these non-prefetchable MU registers. Since non-prefetchable memory windows
cannot be placed above the 4 Gbyte address boundary, when the Prefetchable Indicator bit,
IABAR0[3], is cleared prior to host configuration, also clear the Type Indicator bits, IABAR0[2:1]
for 32-bit addressability. When the non-prefetchable MU registers are in use, those memory
accesses that require prefetchable operations, use the BAR2 configured as prefetchable.
4.
Reading Unpopulated SDRAM Memory Banks
Issue:
A hang condition can occur with the 80219 when firmware does a read to unpopulated SDRAM
memory and DQS0 is sampled low. In this scenario, putting a load (i.e., scope probe), on the DQS0
signal could trigger DQS0 to be sampled low, which the MCU interprets as the pre-amble and waits
for DQS0 to go high. Since the read is to unpopulated memory, nothing drives the DQS0 signal
high, therefore the 80219 appears to hang.
Status:
Doc. Do not attempt to read from non-existent memory. In some applications, firmware performs a
memory scan, typically during boot-up, to determine the total amount o SDRAM installed. Instead,
either use the Serial Presence Detect (SPD) mechanism or have it hard coded in firmware. SPD is
used to read, via I
the DIMM manufacturer, that identifies the module type, various SDRAM organizations and
timing parameters. Using SPD or hard coded firmware eliminates the need to do SDRAM sizing in
the firmware.
5.
32-bit Writes-to-Unaligned 64-bit Addresses, are Promoted to 64-bit Aligned
Writes
Issue:
In 80219-based applications that run the PCI bus segment in 32-bit PCI Mode or 64-bit PCI Mode
with 32-bit targets, write transactions that are on unaligned 64-bit addresses are promoted to 64-bit
aligned writes. The first half of the 64-bit write is on a 64-bit aligned address and has the BE#
signals disabled. Therefore, the write is invalid. The second half on the 64-bit write is a valid write
with the BE# enabled and the write is to the intended 32-bit address.
Per the PCI Local Bus Specification, Revision 2.2, the PCI compliant devices should ignore the
first half of the 64-bit write due to the BE# signals being disabled.
Status:
For devices that support using the I/O memory window, the 64-bit write does not occur when using
the 80219 ATU I/O Window and the only expected 32-bit write occurs. See section 3.2.2.2 of the
®
Intel
80219 General Purpose PCI Processor Developer's Manual for details.
For memory mapped devices, the only option is to run in PCI-X mode, where the byte count and
starting address are consistent with the actual number of bytes to be written (i.e., 4). This is so
because, when a 64-bit PCI-X request gets downshifted, the requester can use the starting
address/byte count to recognize that the write request does not cross a DWORD address boundary
and only perform a single 32-bit wide data cycle.
Specification Update
2
C, from a non-volatile storage device. This device contains data programmed by
®
Intel
80219 General Purpose PCI Processor
Specification Clarifications
27
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