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Intel
80219 General Purpose PCI Processor
Specification Clarifications
Specification Clarifications
1.
The Intel
Local Bus Specification, Revision 2.2 but it is not compliant with PCI Local
Bus Specification, Revision 2.3
Issue:
The Intel
Addendum to the PCI Local Bus Specification, Revision 1.0a, that calls out compliance with the
PCI Local Bus Specification, Revision 2.2. Since the release of the 80219, the PCI Special Interest
Group has released a new specification revision, PCI Local Bus Specification, Revision 2.3.
Status:
NoFix. The current stepping of the 80219 is not compliant with PCI Local Bus Specification,
Revision 2.3 and there are no plans to make it compliant with the PCI Local Bus Specification,
Revision 2.3 in future steppings.
2.
Modifications to the Hot-Debug procedure are necessary for the Intel
80219 general purpose PCI processor when flat memory mapping is not
used (Virtual Address = Physical Address)
Issue:
The Intel
application note "Hot-Debug for Intel
"http://developer.intel.com/design/iio/applnots/273539.htm".
However, there can be a conflict for resources when flat memory mapping is not used (Virtual
Address = Physical Address).
This is primarily due to the debug implementation within the core that causes the Instruction
Memory Management Unit to be disabled when in this Special Debug State.
Status:
NoFix. The following are suggested steps to overcome this conflict within a debug environment.
1. Instrument the application code to add an infinite loop before any memory is remapped
(physically or virtually).
2. Hook up the JTAG Debugger that supports Hot Debug.
3. Set PC to address passed the loop.
4. The code can now run without the need to reset the application environment.
Note: Once a debug session has ended, you must follow the above steps over again in order to regain
debug control.
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®
80219 general purpose PCI processor is compliant with the PCI
®
80219 general purpose PCI processor was designed to be compliant with the PCI-X
®
80219 general purpose PCI processor can implement Hot Debug as stated in the
®
™
Xscale
Core Debug:
®
Specification Update
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