Hardware Layout And Configuration - ST STM3220F-EVAL User Manual

1. Hardware Layout and configuration

The STM3220F-EVAL evaluation board is designed around the STM32F207IFT6 in 176-pin
TQFP package. The hardware block diagram
STM32F207IFT6 and peripherals (Camera module, LCD, PSRAM, OneNAND, EEPROM,
MEMS, USART, IrDA, USB OTG HS, USB OTG FS, Ethernet, Audio, CAN bus, Smart card,
MicroSD card and Motor Control) and
actual evaluation board.
Figure 2: Hardware Block Diagram
1.8V regulator
2.5V regulator
2.8V regulator
3.3V regulator
MCU
consumption
measurement
LEDs,Key
Extension
connector for
GPIOs
OneNAND
PSRAM
TFT LCD
MicroSD
card
MC control
connector
JTAG/SWD
Trace
BNC connector
Potentiometer
Qing SHAO
Figure 2 illustrates the connection between
Figure 3 will help you locate these features on the
GPIO
STM32F207IFT6
FSMC
SDIO
MC
Debug
ADC
Page 4
STM3220F-EVAL Board
USB power
USB HS
OTG HS
PHY
DAC
I2S2
Audio DAC
I2C1
MEMS
EEPROM
IO expandor
Camera
module
DCMI
OTG FS
USB power
switch
MII/RMII PHY
CAN
CAN1
transceiver
CAN
CAN2
transceiver
RS232
transceiver
USART3
IrDA
transceiver
Smart Card
USART6
interface
03/06/2009
switch
USBMicro-AB
connector
Joystick
Touchscreen
USB Micro-AB
connector
Integrated RJ45
connector
CAN
DB9 connector
CAN
DB9 connector
RS232
DB9 connector
Smart Card
connector