Hardware Layout And Configuration; Figure 2. Hardware Block Diagram - ST STM32L073Z-EVAL E User Manual

Hardware layout and configuration

4 Hardware layout and configuration
STM32L073Z-EVAL Evaluation board is designed around the STM32L073VZT6 (LQFP 100
package). The hardware block
between the STM32L073VZT6 and peripherals while
Evaluation board (top view)
board.
Virtual COM
USB Type-B
connector
10/57
Figure 2: Hardware block diagram
helps the user to locate these features on the actual Evaluation

Figure 2. Hardware block diagram

2.4" color
TFT LCD
microSD™
card
LCD segment
40×8
port
Embedded
ST-LINK/V2-1
SWD
connectors
DAC output
ADC input
Touch-sensing slider
4× LEDs
Wake-up / Tamper
button B2
Extension
connectors
for GPIOs
SPI
LCD
USART4
SWD
STM32L073VZ
DAC
ADC
TSC
GPIO
GPIO
MCU
consumption
automeasurement
UM1878 Rev 3
illustrates the connections
Figure 3: STM32L073Z-EVAL
RS-232
transceiver
USART4
IrDA
transceiver
RS-232
LPUART
transceiver
Differential
ADC 16 bits
amplifier
SMB
Temperature
sensor
RF-EEPROM
connector
I2C
Extension
connector
I/O
expander
LP timer
Comparator2
LC sensor
GPIO
USB Micro-B
USB
connector
3.3 V regulator
1.65 V to 3.6 V
adjustable
regulator
VDD_USB
+3.3 V
regulator
UM1878
RS-232
connector
RS-232
connector
Pressure
sensor
Joystick
MSv38506V2