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Monitor software enabling multiple, independent software environments inside a single
platform. Further details on Intel Virtualization Technology can be found at
developer.intel.com/technology/vt.
The Dual-Core Intel
server and workstation systems. The Dual-Core Intel
support a Dual Independent Bus (DIB) architecture with one processor on each bus, up
to two processor sockets in a system. The DIB architecture provides improved
performance by allowing increased FSB speeds and bandwidth. The Dual-Core Intel
®
Xeon
Processor 5100 Series are packaged in an FC-LGA6 Land Grid Array package
with 771 lands for improved power delivery. It utilizes a surface mount LGA771 socket
that supports Direct Socket Loading (DSL).
Table 1-1.
Dual-Core Intel
# of Processor
Cores
2
The Dual-Core Intel
independent core voltage (V
voltage (V
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the Dual-Core Intel
Series. Refer to the appropriate platform design guidelines for implementation details.
The Dual-Core Intel
operation. The Dual-Core Intel® Xeon® Processor LV 5138 and Dual-Core Intel®
Xeon® Processor LV 5128 support 1066MHz Front Side Bus operation. The FSB utilizes
a split-transaction, deferred reply protocol and Source-Synchronous Transfer (SST) of
address and data to improve performance. The processor transfers data four times per
bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the
address bus can deliver addresses two times per bus clock and is referred to as a
'double-clocked' or a 2X address bus. In addition, the Request Phase completes in one
clock cycle. The FSB is also used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1
details are fully described in the appropriate platform design guidelines (refer to
Section
1.3).
1.1
Terminology
A '#' symbol after a signal name refers to an active low signal, indicating a signal is in
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the '#' symbol implies
that the signal is inverted. For example, D[3:0] = 'HLHL' refers to a hex 'A', and
D[3:0]# = 'LHLH' also refers to a hex 'A' (H= High logic level, L= Low logic level).
Commonly used terms are explained here for clarification:
12
®
®
Xeon
Processor 5100 Series are intended for high performance
®
®
Xeon
Processor 5100 Series
L1 Cache
32 KB instruction
32 KB data
®
®
Xeon
Processor 5100 Series based platforms implement
) power planes for each processor. FSB termination
CC
) is shared and must connect to all FSB agents. The processor core voltage
TT
®
®
Xeon
Processor 5100 Series support 1333 MHz Front Side Bus
contains the electrical specifications of the FSB while implementation
®
®
Xeon
L2 Advanced
Front Side Bus
Transfer Cache
Frequencies
1333 MHz
4 MB shared
1066 MHz
®
®
Dual-Core Intel
Xeon
Introduction
http://
Processor 5100 Series
Package
FC-LGA6
771 Lands
®
®
Xeon
Processor 5100
Processor 5100 Series Datasheet
®
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