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Figure 7-1.
Stop Clock State Machine
Normal State
Normal execution
STPCLK#
Asserted
Stop Grant State
BCLK running
Snoops and interrupts allowed
7.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20
bus clocks after the response phase of the processor issued Stop Grant Acknowledge
special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted
once the processor is in the Stop Grant state. Both processor cores will enter the Stop-
Grant state once the STPCLK# pin is asserted. Additionally, both processor cores must
be in the Stop Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should
not be driven (allowing the level to return to V
termination resistors in this state. In addition, all other input pins on the front side bus
should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be
latched and can be serviced by software upon exit from the Stop Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the front side bus (see
94
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
STPCLK#
De-asserted
Snoop Event Occurs
Snoop Event Serviced
Section
7.2.4.1).
Extended HALT or HALT State
BCLK running
Snoops and interrupts allowed
Snoop
Event
Occurs
Extended HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Stop Grant Snoop State
BCLK running
Service snoops to caches
) for minimum power drawn by the
TT
®
®
Dual-Core Intel
Xeon
Processor 5100 Series Datasheet
Features
Snoop
Event
Serviced
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