The Status Byte Status Group - HP E1340A User Manual

The Standard Event
Status Enable Register
The Status Byte
Status Group
The Status Byte
Register
Chapter 8
The Standard Event Status Enable Register specifies which bits in the
Standard Event Status Register can generate a summary bit which is
subsequently used to generate a service request. The AFG logically ANDs
the bits in the Event Register with bits in the Enable Register, and ORs the
results to obtain a summary bit.
The bits in the Enable Register that are to be ANDed with bits in the Event
Register are specified (unmasked) with the command:
*ESE < unmask >
unmask is the decimal, hexadecimal (#H), octal (#Q), or binary (#B)
< >
value of the Enable Register bit to be unmasked. (Bits 7, 5, 4, 3, 2, 0 have
corresponding decimal values of 128, 32, 16, 8, 4, 1.)
All unmasked bits in the Enable Register can be determined with the
command:
*ESE?
The Standard Event Status Enable Register is cleared at power-on, or with
an unmask value of 0.
< >
The registers in the Status Byte Status Group enable conditions monitored
by the other status groups to generate a service request.
The Status Byte Register contains the summary bits of the Questionable
Signal Status Group (
Standard Event Status Group (
available bit (
MAV
7 6 5
OPER RQS ESB
Questionable Signal Summary Bit (QUES):
condition monitored by the Questionable Signal Status Group is present,
when the appropriate bit is latched into the group's Event Register, and
when the bit is unmasked by the group's Enable Register.
Message Available Bit (MAV):
response, is in the AFG's output queue.
Standard Event Summary Bit (ESB):
monitored by the Standard Event Status Group is present and the
appropriate bit is set in the group's Event Register, and when the bit is
unmasked by the group's Enable Register.
Service Request Bit (RQS):
Byte Register is set.
QUES ), the Operation Status Group (
ESB ). The register also contains the message
) and the service request bit (
4 3
MAV QUES
Bit 4 is set (1) when data, such as a query
Bit 5 is set (1) when a condition
Bit 6 is set (1) when any other bit in the Status
HP E1340A AFG Status
OPER ), and the
).
RQS
2 1
unused
Bit 3 is set (1) when a
0
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