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STATus
Operation Status
Register
Questionable Signal
Status Register
Subsystem Syntax
Chapter 7
The
STATus
subsystem controls the SCPI-defined Operation and
Questionable Signal Status Registers. Each is comprised of a Condition
Register, an Event Register, an enable mask, and negative and positive
transition filters.
Each Status Register works as follows: when a condition occurs, the
appropriate bit in the Condition Register is set or cleared. If the the
corresponding transition filter is enabled for that bit, the same bit is set in
the associated Event Register. The contents of the Event Register and the
enable mask are logically ANDed bit-for-bit; if any bit of the result is set,
the summary bit for that register is set in the status byte. The status byte
summary bit for the Operation Status Register is bit 7; for the Questionable
Signal Status Register, bit 3.
Only bits 0 (
CALibrating
the HP E1340A. All other bits are always zero.
Bit 0 - CALibrating:
otherwise.
Bit 3 - SWEeping:
progress. Cleared (0) when waveform generation is halted, when
frequency sweeping or lists are not selected, and at the end of each
sweep or list.
Bit 8 - INITiated:
Cleared (0) by the
burst of waveform repetitions (
ARM:LAYer1:COUNt
other command executed after waveform generation completes.
All bits are always 0. This register is implemented only for SCPI
compatibility purposes.
STATus
:OPERation|QUEStionable
:CONDition?
:ENABle <
unmask
[:EVENt]?
:NTRansition <
:PTRansition <
:PRESet
STATus[:LEVel][:IMMediate]:OFFSet
), 3 (
SWEeping
), and 8 (
Set (1) during calibration. Cleared (0)
Set (1) while a frequency sweep or list is in
Set (1) by the
INITiate:IMMediate
command. When outputting a single
ABORt
ARM:LAYer2:COUNt 1
not set to
INFinity
), it is also cleared by any
[query only]
>
[query only]
unmask
>
unmask
>
[no query]
HP E1340A Command Reference
INITiated
) are defined for
command.
set and
181
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