Board Layout - Intergraph InterServe 8000 System Reference Manual

Board Layout

VRM 3
VRM 1
Memory Sockets
PCI Bridge
Two PCI bridge chips (Intel OPB 0 82454) provide high-bandwidth PCI compatibility for the system.
One bridge chip supports PCI bus 0 (Primary Compatibility bus), and is the path by which processors
have access to all PC compatibility devices such as the ISA bus, BIOS PROM, and graphics controller.
PCI bus 0 supports slots 1 through 3. PCI bus 1 (Primary Auxiliary bus) is also bridged directly off the
P6 bus by the second 82454 and supports PCI slots 4 through 7. For best system performance, high-
bandwidth devices that efficiently use PCI burst protocols to transfer data as bus masters should reside
on PCI bus 0 or 1 (slots 1 through 7).
NOTE The remaining PCI slots (8 through 10) are supported by the DEC 21050 on the I/O expansion board.
Lithium Battery
The Lithium battery on the processor board provides power to the Real Time Clock, which the
MSMT332 board uses to display the current time on the LCD screen. As long as the system is running,
the batteries are not used to sustain the information. If the battery fails, the LCD screen will not display
the date and time.
PCI Connector 0 Sideband Connector
CPU 3 CPU 1
J17 J18
OPB 0
(Primary
Compatibility)
82454
PCI Connector 1
CPU 0 CPU 2
J19 J20
OPB 0
(Primary
Auxiliary)
82454
Memory Sockets
51
VRM 0
VRM 2
Lithium
Battery