Cisco CRS-1 - Carrier Routing System Router Migration Manual page 193

Chapter 3 Cisco CRS-3 Carrier Routing System Router Command Changes
Table 7
Field
spi4_tx_frames:
DeviceID
RevisionID
SideBandFC
SERDESGlbCntl
GlblEPDCntlCfg
TxFIFOUrecECCErrCtr
RxFIFOUrecECCErrCtr
DeviceGlobalRst
GlobalCfg
PortTest
PL4IOGlblStat
DeviceTest
MACStatus Port0
MACControl0 Port0
MACControl1 Port0
MACControl2 Port0
SERDESCntl Port0
RateLimCntl Port0
SysIntMask
SysIntCause
GOPIntMask0
OL-13669-03
show controllers GigabitEthernet Field Descriptions
Description
SPI-4/1 transmit frame count. This counter increments once for
every packet arriving on the SPI-4.2 receive interface.
Note
Unique number identifying the device.
Indicates the revision of the device.
Indicates whether serial sideband flow control is enabled on this
port, and the status of ports where flow control is currently active.
Displays information about SERDES speed and receive (Rx) Gain
on this port.
Cisco-specific register that shows whether Ethernet Packet
Decoding is enabled.
Transmit (Tx) FIFO unrecoverable ECC errors counter. This
counter increments once per each ECC unrecoverable error. A
masked interrupt is optionally generated.
Receive (Rx) FIFO unrecoverable ECC errors counter. This counter
increments once per each ECC unrecoverable error. A masked
interrupt is optionally generated.
Global register that controls device reset state.
Global register that controls enable, clock modes, and Rx Interface
behavior.
Port diagnostics register.
Register used during SPI4.2 initialization.
Diagnostic loopback register.
MAC control port register.
MAC control port register. Indicates whether the port is enabled on
this port, and the status of flow control on this port.
MAC control port1 register. Indicates whether the port is enabled on
this port, and the status of flow control on this port.
MAC control port2 register. Indicates whether the port is enabled on
this port, and the status of flow control on this port.
SERDES control port register. The following information is
displayed:
• 0 = 50 Ohm
• 1 = 75 Ohm
Rate Limit control port 10 register.
When the matching bit in the mask register is reset, the matching
interrupt in the cause register is not included in the sum.
Register that tracks the causes of system interrupts.
GOP interrupt Mask0. When the matching bit in the mask register
is reset, the matching cause in the GOP register is not included in
the sum.
Cisco CRS-1 Carrier Routing System to Cisco CRS-3 Carrier Routing System Migration Guide
Packets that contain certain types of errors and packets sent
to the CPU are not counted.
show controllers (Ethernet)
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