Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 168

Operation: if (PR[qp]) {
size = (fill_form ? 16 : (integer_form ? 8 : fsz));
speculative = (fldtype == 's' || fldtype == 'sa');
advanced = (fldtype == 'a' || fldtype == 'sa');
check_clear = (fldtype == 'c.clr' );
check_no_clear = (fldtype == 'c.nc');
check = check_clear || check_no_clear;
translate_address = 1;
read_memory = 1;
itype = READ;
if (speculative) itype |= SPEC;
if (advanced) itype |= ADVANCE;
if (size == 10) itype |= UNCACHE_OPT;
if (reg_base_update_form || imm_base_update_form)
check_target_register(r
fp_check_target_register(f
if (tmp_isrcode = fp_reg_disabled(f
disabled_fp_register_fault(tmp_isrcode, itype);
if (!speculative && GR[r
register_nat_consumption_fault(itype);
defer = speculative && (GR[r
if (check && alat_cmp(FLOAT, f
translate_address = alat_translate_address_on_hit(fldtype, FLOAT, f
read_memory = alat_read_memory_on_hit(fldtype, FLOAT, f
}
if (!translate_address) {
if (check_clear || advanced)
} else {
if (!defer) {
}
if (check_clear || advanced)
if (speculative && defer) {
} else if (advanced && !speculative && defer) {
} else {
}
Volume 3: Instruction Reference
);
3
);
1
].nat)
3
alat_inval_single_entry(FLOAT, f
paddr = tlb_translate(GR[r
spontaneous_deferral(paddr, size, UM.be, mattr, UNORDERED,
if (!defer && read_memory)
val = mem_read(paddr, size, UM.be, mattr, UNORDERED, ldhint);
alat_inval_single_entry(FLOAT, f
FR[f ] = NATVAL;
1
FR[f ] = (integer_form ? FP_INT_ZERO : FP_ZERO);
1
FR[f ] = fp_mem_to_fr_format(val, size, integer_form);
1
if ((check_no_clear || advanced) && ma_is_speculative(mattr))
alat_write(fldtype, FLOAT, f
, 0, 0, 0))
1
// fault on NaT address
].nat || PSR.ed);// defer exception if spec
3
)) {
1
// remove any old ALAT entry
);
1
], size, itype, PSR.cpl, &mattr,
3
&defer);
ldhint, &defer);
// remove any old ALAT entry
);
1
// execute load normally
// add entry to ALAT
, paddr, size);
1
ldf
);
1
);
1
3:159