Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 164
Architecture software developer's manual revision 2.3
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}
if (check_clear || advanced)
if (defer) {
} else {
}
}
if (imm_base_update_form) {
GR[r
GR[r
} else if (reg_base_update_form) {
GR[r
GR[r
}
if ((reg_base_update_form || imm_base_update_form) && !GR[r
mem_implicit_prefetch(GR[r
}
Volume 3: Instruction Reference
val = mem_read(paddr, size, UM.be, mattr, otype,
}
}
alat_inval_single_entry(GENERAL, r
if (speculative) {
GR[r
] = natd_gr_read(paddr, size, UM.be, mattr, otype,
1
GR[r
].nat = 1;
1
} else {
GR[r
] = 0;
1
GR[r
].nat = 0;
1
}
if (fill_form) {
bit_pos = GR[r
]{8:3};
3
GR[r
] = val;
1
GR[r
].nat = AR[UNAT]{bit_pos};
1
} else {
if (size == 16) {
GR[r
] = val;
1
AR[CSD] = val_ar;
}
else {
GR[r
] = zero_ext(val, size * 8);
1
}
GR[r
].nat = 0;
1
}
if ((check_no_clear || advanced) && ma_is_speculative(mattr))
alat_write(ldtype, GENERAL, r
] = GR[r
] + sign_ext(imm
3
3
].nat = GR[r
].nat;
3
3
] = GR[r
] + tmp_r2;
3
3
].nat = GR[r
].nat || tmp_r2nat;
3
3
bias | ldhint);
// remove any old ALAT entry
);
1
bias | ldhint);
// ld.a to sequential memory
// execute load normally
// fill NaT on ld8.fill
// clear NaT on other types
// add entry to ALAT
, paddr, size);
1
// update base register
, 9);
9
], ldhint | bias, itype);
3
ld
].nat)
3
3:155
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