Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 239

ptc.e
ptc.e — Purge Translation Cache Entry
( ) ptc.e r
Format: qp
One or more translation entries are purged from the local processor's instruction and
Description:
data translation cache. Translation Registers and the VHPT are not modified.
The number of translation cache entries purged is implementation specific. Some
implementations may purge all levels of the translation cache hierarchy with one
iteration of PTC.e, while other implementations may require several iterations to flush
all levels, sets and associativities of both instruction and data translation caches. GR r
specifies an implementation-specific parameter associated with each iteration.
The following loop is defined to flush the entire translation cache for all processor
models. Software can acquire parameters through a processor dependent layer that is
accessed through a procedural interface. The selected region registers must remain
unchanged during the loop.
disable_interrupts();
addr = base;
for (i = 0; i < count1; i++) {
}
enable_interrupts();
This instruction can only be executed at the most privileged level, and when PSR.vm is
0.
Operation: if (PR[qp]) {
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (GR[r
register_nat_consumption_fault(0);
if (PSR.vm == 1)
virtualization_fault();
tlb_purge_translation_cache(GR[r
}
Privileged Operation fault
Interruptions:
Register NaT Consumption fault
Software must issue a data serialization operation to ensure the purge is complete
Serialization:
before issuing a data access or non-access reference dependent upon the purge.
Software must issue instruction serialize operation before fetching an instruction
dependent upon the purge.
3:230
3
for (j = 0; j < count2; j++) {
ptc.e(addr);
addr += stride2;
}
addr += stride1;
].nat)
3
]);
3
Virtualization fault
Volume 3: Instruction Reference
M47
3