Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 156

itc — Insert Translation Cache
( ) itc.i
Format: qp r
2
( ) itc.d
qp r
An entry is inserted into the instruction or data translation cache. GR
Description:
physical address portion of the translation. ITIR specifies the protection key, page size
and additional information. The virtual address is specified by the IFA register and the
region register is selected by IFA{63:61}. The processor determines which entry to
replace based on an implementation-specific replacement algorithm.
The visibility of the itc instruction to externally generated purges (ptc.g, ptc.ga)
must occur before subsequent memory operations. From a software perspective, this is
similar to acquire semantics. Serialization is still required to observe the side-effects of
a translation being present.
itc must be the last instruction in an instruction group; otherwise, its behavior
(including its ordering semantics) is undefined.
The TLB is first purged of any overlapping entries as specified by
page 2:52.
This instruction can only be executed at the most privileged level, and when PSR.ic and
PSR.vm are both 0.
To ensure forward progress, software must ensure that PSR.ic remains 0 until rfi-ing
to the instruction that requires the translation.
Volume 3: Instruction Reference
2
itc
instruction_form M41
data_form M41
specifies the
r
2
Table 4-1 on
3:147