Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 93

fmix
Operation: if (PR[qp]) {
fp_check_target_register(f
if (tmp_isrcode = fp_reg_disabled(f
disabled_fp_register_fault(tmp_isrcode, 0);
if (fp_is_natval(FR[f
FR[f
} else {
if (mix_l_form) {
} else if (mix_r_form) {
} else {
}
FR[f
FR[f
FR[f
}
fp_update_psr(f
}
None
FP Exceptions:
Illegal Operation fault
Interruptions:
3:84
);
1
]) || fp_is_natval(FR[f
2
] = NATVAL;
1
tmp_res_hi = FR[f ].significand{63:32};
2
tmp_res_lo = FR[f ].significand{63:32};
3
tmp_res_hi = FR[f ].significand{31:0};
2
tmp_res_lo = FR[f ].significand{31:0};
3
tmp_res_hi = FR[f ].significand{63:32};
2
tmp_res_lo = FR[f ].significand{31:0};
3
].significand = fp_concatenate(tmp_res_hi, tmp_res_lo);
1
].exponent = FP_INTEGER_EXP;
1
].sign = FP_SIGN_POSITIVE;
1
);
1
, f , f , 0))
1 2 3
])) {
3
// mix_lr_form
Disabled Floating-point Register fault
Volume 3: Instruction Reference