Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 158

itr — Insert Translation Register
( ) itr.i itr[
Format: qp
( ) itr.d dtr[
qp
A translation is inserted into the instruction or data translation register specified by the
Description:
contents of GR
specifies the protection key, page size and additional information. The virtual address is
specified by the IFA register and the region register is selected by IFA{63:61}.
As described in
the TLB is first purged of any entries that overlap with the newly inserted translation.
The translation previously contained in the TR slot specified by GR
purged from the processor's TLBs and may remain as a TC entry. To ensure that the
previous TR translation is purged, software must use explicit ptr instructions before
inserting the new TR entry.
This instruction can only be executed at the most privileged level, and when PSR.ic and
PSR.vm are both 0.
Operation: if (PR[qp]) {
if (PSR.ic)
illegal_operation_fault();
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (GR[r
register_nat_consumption_fault(0);
slot = GR[r
tmp_size = CR[ITIR].ps;
tmp_va = CR[IFA]{60:0};
tmp_rid = RR[CR[IFA]{63:61}].rid;
tmp_va = align_to_size_boundary(tmp_va, tmp_size);
tmp_tr_type = instruction_form ? ITR_TYPE : DTR_TYPE;
if (is_reserved_reg(tmp_tr_type, slot))
reserved_register_field_fault();
if (is_reserved_field(TLB_TYPE, GR[r
reserved_register_field_fault();
if (!impl_check_mov_ifa() &&
unimplemented_data_address_fault(0);
if (PSR.vm == 1)
virtualization_fault();
if (instruction_form) {
tlb_must_purge_itc_entries(tmp_rid, tmp_va, tmp_size);
tlb_may_purge_dtc_entries(tmp_rid, tmp_va, tmp_size);
tlb_insert_inst(slot, GR[r
} else {
tlb_must_purge_dtc_entries(tmp_rid, tmp_va, tmp_size);
tlb_may_purge_itc_entries(tmp_rid, tmp_va, tmp_size);
tlb_insert_data(slot, GR[r
}
}
Volume 3: Instruction Reference
] =
r r
3 2
] =
r r
3 2
. GR specifies the physical address portion of the translation. ITIR
r r
3 2
Table 4-1, "Purge Behavior of TLB Inserts and Purges" on page
].nat || GR[r ].nat)
3 2
]{7:0};
3
unimplemented_virtual_address(CR[IFA], PSR.vm))
], CR[ITIR]))
2
], CR[ITIR], CR[IFA], tmp_rid, TR);
2
// data_form
], CR[ITIR], CR[IFA], tmp_rid, TR);
2
itr
instruction_form M42
data_form M42
2:52,
is not necessarily
r
3
3:149