Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 53

cmp4
Operation: if (PR[qp]) {
if (p
illegal_operation_fault();
tmp_nat = (register_form ? GR[r
if (register_form)
tmp_src = GR[r
else if (imm8_form)
tmp_src = sign_ext(imm
else // parallel_inequality_form
tmp_src = 0;
if
else if (crel == 'ne')
else if (crel == 'lt')
tmp_rel = lesser_signed(sign_ext(tmp_src, 32),
else if (crel == 'le')
tmp_rel = lesser_equal_signed(sign_ext(tmp_src, 32),
else if (crel == 'gt')
tmp_rel = greater_signed(sign_ext(tmp_src, 32),
else if (crel == 'ge')
tmp_rel = greater_equal_signed(sign_ext(tmp_src, 32),
else if (crel == 'ltu')
tmp_rel = lesser(zero_ext(tmp_src, 32),
else if (crel == 'leu')
tmp_rel = lesser_equal(zero_ext(tmp_src, 32),
else if (crel == 'gtu')
tmp_rel = greater(zero_ext(tmp_src, 32),
else
tmp_rel = greater_equal(zero_ext(tmp_src, 32),
switch (ctype) {
case 'and':
case 'or':
case 'or.andcm':
3:44
== p )
1 2
];
2
8
(crel == 'eq') tmp_rel = tmp_src{31:0} == GR[r
tmp_rel = tmp_src{31:0} != GR[r
// 'geu'
if (tmp_nat || !tmp_rel) {
PR[p ] = 0;
1
PR[p ] = 0;
2
}
break;
if (!tmp_nat && tmp_rel) {
PR[p ] = 1;
1
PR[p ] = 1;
2
}
break;
if (!tmp_nat && tmp_rel) {
PR[p ] = 1;
1
].nat : 0) || GR[r
2
, 8);
sign_ext(GR[r ], 32));
3
sign_ext(GR[r ], 32));
3
sign_ext(GR[r ], 32));
3
sign_ext(GR[r ], 32));
3
zero_ext(GR[r ], 32));
3
zero_ext(GR[r ], 32));
3
zero_ext(GR[r ], 32));
3
zero_ext(GR[r ], 32));
3
].nat;
3
]{31:0};
3
]{31:0};
3
// and-type compare
// or-type compare
// or.andcm-type compare
Volume 3: Instruction Reference