Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 190

if (from_form) {
check_target_register(r
if (PSR.cpl != 0 && !(ireg == PMD_TYPE || ireg == CPUID_TYPE))
if (GR[r
if (is_reserved_reg(ireg, tmp_index))
if (PSR.vm == 1 && ireg != PMD_TYPE)
if (ireg == PMD_TYPE) {
} else
GR[r
} else {
if (PSR.cpl != 0)
if (GR[r
if (is_reserved_reg(ireg, tmp_index)
if (PSR.vm == 1)
if (ireg == PKR_TYPE && GR[r
}
tmp_val = ignored_field_mask(ireg, tmp_index, GR[r
switch (ireg) {
Volume 3: Instruction Reference
);
1
privileged_operation_fault(0);
].nat)
3
register_nat_consumption_fault(0);
reserved_register_field_fault();
virtualization_fault();
if ((PSR.cpl != 0) && ((PSR.sp == 1) ||
(tmp_index > 3 &&
tmp_index <= IMPL_MAXGENERIC_PMCPMD &&
PMC[tmp_index].pm == 1)))
GR[r ] = 0;
1
else
GR[r ] = pmd_read(tmp_index);
1
switch (ireg) {
case CPUID_TYPE: GR[r
case DBR_TYPE:
case IBR_TYPE:
case PKR_TYPE:
case PMC_TYPE:
case RR_TYPE:
}
].nat = 0;
1
// to_form
privileged_operation_fault(0);
].nat || GR[r ].nat)
2 3
register_nat_consumption_fault(0);
|| ireg == CPUID_TYPE
|| is_reserved_field(ireg, tmp_index, GR[r
reserved_register_field_fault();
virtualization_fault();
if ((tmp_slot = tlb_search_pkr(GR[r
PKR[tmp_slot].v = 0; // clear valid bit of matching key reg
case DBR_TYPE: DBR[tmp_index] = tmp_val; break;
case IBR_TYPE: IBR[tmp_index] = tmp_val; break;
case PKR_TYPE: PKR[tmp_index] = tmp_val; break;
case PMC_TYPE: pmc_write(tmp_index, tmp_val); break;
] = CPUID[tmp_index]; break;
1
GR[r ] = DBR[tmp_index]; break;
1
GR[r ] = IBR[tmp_index]; break;
1
GR[r ] = PKR[tmp_index]; break;
1
GR[r ] = pmc_read(tmp_index); break;
1
GR[r ] = RR[tmp_index]; break;
1
]{0} == 1) { // writing valid prot key
2
]{31:8})) != NOT_FOUND)
2
mov indirect
]))
2
]);
2
3:181