Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 233

pshr
pshr — Parallel Shift Right
( ) pshr2
Format: qp
( ) pshr2
qp
( ) pshr2.u
qp
( ) pshr2.u
qp
( ) pshr4
qp
( ) pshr4
qp
( ) pshr4.u
qp
( ) pshr4.u
qp
The data elements of GR
Description:
shift count in GR
element are filled with either the initial value of the sign bits of the data elements in GR
(arithmetic shift) or zeros (logical shift). The shift count is interpreted as unsigned.
r
3
Shift counts greater than 15 (for 16-bit quantities) or 31 (for 32-bit quantities) yield all
zero or all one results depending on the initial values of the sign bits of the data
elements in GR
in GR .
r
1
3:224
= ,
r r r
1 3 2
= , count
r r
1 3 5
= ,
r r r
1 3 2
= , count
r r
1 3 5
= ,
r r r
1 3 2
= , count
r r
1 3 5
= ,
r r r
1 3 2
= , count
r r
1 3 5
are each independently shifted to the right by the scalar
r
3
, or in the immediate field count
r
2
and whether a signed or unsigned shift is done. The results are placed
r
3
signed_form, two_byte_form, variable_form
signed_form, two_byte_form, fixed_form
unsigned_form, two_byte_form, variable_form
unsigned_form, two_byte_form, fixed_form
signed_form, four_byte_form, variable_form
signed_form, four_byte_form, fixed_form
unsigned_form, four_byte_form, variable_form
unsigned_form, four_byte_form, fixed_form
. The high-order bits of each
5
Volume 3: Instruction Reference
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I6
I5
I6
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I6
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