Table Of Contents - Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet

Contents
1 Introduction ............................................................................................................ 11
1.1 Terminology ..................................................................................................... 12
1.1.1 Processor Terminology Definitions ............................................................ 12
1.2 References ....................................................................................................... 14
2 Electrical Specifications ........................................................................................... 15
2.1 Power and Ground Lands.................................................................................... 15
2.2 Decoupling Guidelines ........................................................................................ 15
2.2.1 VCC Decoupling ..................................................................................... 15
2.2.2 Vtt Decoupling ....................................................................................... 15
2.2.3 FSB Decoupling...................................................................................... 16
2.3 Voltage Identification ......................................................................................... 16
2.4 Reserved, Unused, and TESTHI Signals ................................................................ 18
2.5 Power Segment Identifier (PSID)......................................................................... 18
2.6 Voltage and Current Specification ........................................................................ 19
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 19
2.6.2 DC Voltage and Current Specification ........................................................ 20
2.6.3 VCC Overshoot ...................................................................................... 25
2.6.4 Die Voltage Validation ............................................................................. 25
2.7 Signaling Specifications...................................................................................... 26
2.7.1 FSB Signal Groups.................................................................................. 26
2.7.2 CMOS and Open Drain Signals ................................................................. 28
2.7.3 Processor DC Specifications ..................................................................... 28
2.7.3.1
2.7.3.2
2.8 Clock Specifications ........................................................................................... 31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 32
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 32
2.8.4 BCLK[1:0] Specifications ......................................................................... 32
3 Package Mechanical Specifications .......................................................................... 35
3.1 Package Mechanical Drawing............................................................................... 35
3.2 Processor Component Keep-Out Zones ................................................................. 39
3.3 Package Loading Specifications ........................................................................... 39
3.4 Package Handling Guidelines............................................................................... 39
3.5 Package Insertion Specifications.......................................................................... 40
3.6 Processor Mass Specification ............................................................................... 40
3.7 Processor Materials............................................................................................ 40
3.8 Processor Markings............................................................................................ 40
4 Land Listing and Signal Descriptions ....................................................................... 43
4.1 Processor Land Assignments ............................................................................... 43
4.2 Alphabetical Signals Reference ............................................................................ 64
5 Thermal Specifications and Design Considerations .................................................. 75
5.1 Processor Thermal Specifications ......................................................................... 75
5.1.1 Thermal Specifications ............................................................................ 75
5.1.2 Thermal Metrology ................................................................................. 82
5.2 Processor Thermal Features ................................................................................ 82
5.2.1 Thermal Monitor..................................................................................... 82
5.2.2 Thermal Monitor 2 .................................................................................. 83
Datasheet
Platform Environment Control Interface (PECI) DC Specifications..... 29
GTL+ Front Side Bus Specifications ............................................. 30
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