Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet page 55

Land Listing and Signal Descriptions
Table 4-2.
Land
Land Name
#
VTT_OUT_RI
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
AB2 IERR#
AB3
AB4
AB5
AB6
AB7
AB8
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC1
AC2
AC3
AC4 RESERVED
AC5
AC6
AC7
AC8
AC23
AC24
AC25
AC26
AC27
Datasheet
Numerical Land
Assignment
Signal Buffer
Direction
Type
Power/Other
GHT
FC39 Power/Other
VSS Power/Other
A21# Source Synch Input/Output
A23# Source Synch Input/Output
VSS Power/Other
VSS Power/Other
VCC Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
Asynch CMOS
FC37 Power/Other
A26# Source Synch Input/Output
A24# Source Synch Input/Output
A17# Source Synch Input/Output
VSS Power/Other
VCC Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
TMS TAP
DBR# Power/Other
VSS Power/Other
A25# Source Synch Input/Output
VSS Power/Other
VSS Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
Table 4-2.
Land
Land Name
#
AC28 VCC
Output
AC29 VCC
AC30 VCC
AD1 TDI
AD2 BPM2#
AD3 FC36
AD4 VSS
AD5 ADSTB1#
AD6 A22#
AD7 VSS
AD8 VCC
AD23 VCC
AD24 VCC
AD25 VCC
AD26 VCC
AD27 VCC
AD28 VCC
AD29 VCC
Output
AD30 VCC
AE1 TCK
AE2 VSS
AE3 FC18
AE4 RESERVED
AE5 VSS
AE6 RESERVED
AE7 VSS
AE8 SKTOCC#
AE9 VCC
AE10 VSS
AE11 VCC
AE12 VCC
AE13 VSS
AE14 VCC
Input
AE15 VCC
Output
AE16 VSS
AE17 VSS
AE18 VCC
AE19 VCC
AE20 VSS
AE21 VCC
AE22 VCC
AE23 VCC
AE24 VSS
AE25 VSS
AE26 VSS
AE27 VSS
Numerical Land
Assignment
Signal Buffer
Direction
Type
Power/Other
Power/Other
Power/Other
TAP Input
Common Clock Input/Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
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