Signaling Specifications; Fsb Signal Groups - Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet

2.7

Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as V
separate power planes for each processor (and chipset), separate V
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see
GTL+ signals are provided on the processor silicon and are terminated to V
chipsets will also provide on-die termination; thus, eliminating the need to terminate
the bus on the motherboard for most GTL+ signals.
2.7.1

FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[3:0] as a reference level. In
this document, the term "GTL+ Input" refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle.
and asynchronous.
Table 2-6. FSB Signal Groups (Sheet 1 of 2)
Signal Group
GTL+ Common
Clock Input
GTL+ Common
Clock I/O
GTL+ Source
Synchronous I/O
26
Table 2-13 for GTLREF specifications). Termination resistors (R
Table 2-6 identifies which signals are common clock, source synchronous,
Type
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
Synchronous to
assoc. strobe
. Because platforms implement
TT
Signals
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#
DRDY#, HIT#, HITM#, LOCK#
Signals
3
REQ[4:0]#, A[16:3]#
3
A[35:17]#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Electrical Specifications
and V supplies
CC TT
) for
TT
. Intel
TT
1
3
, DBSY#,
Associated Strobe
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Datasheet