Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet page 65

Land Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 2 of 10)
Name
BPM[5:0]#
BPMb[3:0]#
BPRI#
BR0#
BSEL[2:0]
COMP[3:0],
COMP8
Datasheet
Type
BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint
and performance monitor signals. They are outputs from the
processor which indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. BPM[5:0]# and BPMb[3:0]# should connect the
appropriate pins/lands of all processor FSB agents. BPM[3:0]# are
associated with core 0. BPMb[3:0]# are associated with core 1.
Input/
BPM4# provides PRDY# (Probe Ready) functionality for the TAP
Output
port. PRDY# is a processor output used by debug tools to
determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of
the processor.
These signals do not have on-die termination. Refer to
Section 2.6.2 for termination requirements.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the processor FSB. It must connect the appropriate pins/lands of
all processor FSB agents. Observing BPRI# active (as asserted by
the priority agent) causes all other agents to stop issuing new
Input
requests, unless such requests are part of an ongoing locked
operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by de-asserting
BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
Input/
signal is sampled to determine the agent ID = 0.
Output
This signal does not have on-die termination and must be
terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to
select the processor input clock frequency.
possible combinations of the signals and the frequency associated
with each combination. The required frequency is determined by
Output
the processor, chipset and clock synthesizer. All agents must
operate at the same frequency. For more information about these
signals, including termination recommendations refer to
Section 2.8.2.
COMP[3:0] and COMP8 must be terminated to V
Analog
board using precision resistors.
Description
Table 2-15
on the system
SS
defines the
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