Quad-Pumped Signal Groups; Dinv[3:0]# Assignment To Data Bus - Intel Pga478 - P4-2ghz 512kb 400mhz Fsb Datasheet

Intel celeron processor 1.66 ghz/1.83 ghz

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Table Of Contents

Table of Contents

Table 11.

Signal Description (Sheet 3 of 7)

Name

D[63:0]#

DBSY#

DEFER#

DP[3:0]#

DINV[3:0]#

DRDY#

Intel

Celeron

Processor 1.66 GHz/1.83 GHz

Intel

Celeron

Processor 1.66 GHz/1.83 GHz—Package Mechanical Specifications and Pin

Type

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the FSB agents, and must connect the appropriate pins on both agents.

The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and is thus be driven four times in a

common clock period. D[63:0]# are latched off the falling edge of both

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a

pair of one DSTBP# and one DSTBN#. The following table shows the grouping of

data signals to data strobes and DINV#.

Table 12.

Data Group

Input/

Output

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

Furthermore, the DINV# pins determine the polarity of the data signals. Each

group of 16 data signals corresponds to one DINV# signal. When the DINV#

signal is active, the corresponding data group is inverted and therefore sampled

active high.

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on

Input/

the FSB to indicate that the data bus is in use. The data bus is released after

Output

DBSY# is deasserted. This signal must connect the appropriate pins on both FSB

agents.

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the

Input

responsibility of the addressed memory or Input/Output agent. This signal must

connect the appropriate pins of all FSB agents.

Input/

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They

Output

are driven by the agent responsible for driving D[63:0]#, and must connect the

appropriate pins of all processor front side bus agents.

DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the

polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the

data on the data bus is inverted. The bus agent inverts the data bus signals if

more than half the bits, within the covered group, change level in the next cycle.

Table 13.

Bus Signal

Input/

Output

DINV[3]#

DINV[2]#

DINV[1]#

DINV[0]#

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

Input/

indicating valid data on the data bus. In a multi-common clock data transfer,

Output

DRDY# may be deasserted to insert idle clocks. This signal must connect the

appropriate pins of both FSB agents.

Description