Intel Pga478 - P4-2ghz 512kb 400mhz Fsb Datasheet page 34

Table 11. Signal Description (Sheet 5 of 7)
Name
IGNNE#
INIT#
LINT[1:0]
LOCK#
MCERR#
ODTEN
PRDY#
PREQ#
® ®
Intel Celeron Processor 1.66 GHz/1.83 GHz
DS
34
® ®
Intel Celeron Processor 1.66 GHz/1.83 GHz—Package Mechanical Specifications and Pin
Type
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute non-control floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
Input
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the
TRDY# assertion of the corresponding Input/Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside the
processor without affecting its internal caches or floating-point registers. The
processor then begins execution at the power-on Reset vector configured during
power-on configuration. The processor continues to handle snoop requests
Input
during INIT# assertion. INIT# is an asynchronous signal. However, to ensure
recognition of this signal following an Input/Output Write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/Output Write
bus transaction. INIT# must connect the appropriate pins of both FSB agents.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC
Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those
names on the Intel
Input
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the
APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is
the default configuration.
LOCK# indicates to the system that a transaction must occur atomically. This
signal must connect the appropriate pins of both FSB agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
Input/
Output
When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it
waits until it observes LOCK# deasserted. This enables symmetric agents to
retain ownership of the FSB throughout the bus locked operation and ensure the
atomicity of lock.
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor front side bus
agents. MCERR# assertion conditions are configurable at a system level.
Assertion options are defined by the following options:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it
Input/
observes an error.
Output
• Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the
and IA-32 Architectures Software Developer's Manuals
System Programming
Since multiple agents may drive this signal at the same time, MCERR# is a wire-
OR signal which must connect the appropriate pins of all processor front side bus
agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, MCERR# is activated on specific clock
edges and sampled on specific clock edges.
ODTEN (On-die termination enable) should be connected to V
termination for end bus agents. Intel
Input always the end bus agent because it supports uniprocessor configurations only.
Whenever ODTEN is high, on-die termination is active, regardless of other states
of the bus.
Probe Ready signal used by debug tools to determine processor debug
Output
readiness.
Probe Request signal used by debug tools to request debug operation of the
Input
processor.
Description
® ®
Pentium processor. Both signals are asynchronous.
Guide.
® ®
Celeron Processor 1.66 GHz/1.83 GHz is
Information
Intel® 64
in Volume 3A/3B:
to enable on-die
CC
January 2007
Order Number: 315876-002