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DIDS-402-2AMl3
4-16. 1 Transmit Mode
In the transmit mode, the buffer registers are used to release a steady
stream of serial bit data at the l200-baud transmission rate.
As data is recircu-
lated in the refresh memory 63 times a second, the cursor appears in the CTS
flip-flop of the character entry register every 16.026 ms.
Each time the cursor
appears, data can be extracted from the refresh memory loop and shifted into the
buffer registers for transmission to the CPU.
If only one character were extracted each time the cursor appeared, the
maximum transmission rate would be 63 characters/ second.
To achieve the
desired 120 character / second rate, at least one, and usually two, characters
must be extracted each time the memory is accessed.
The purpose of the buffer
registers is to temporarily hold these characters until they can be shifted out
to the CPU by the l200-baud circuitry.
To initiate data messages, display terminal operators type in the desired
text and then depress the END key.
The END key places an ETX code in memory
and enables the XMIT key.
When XMIT is then depressed, a signal is developed
which jams STX into buffer register D3 and the correct DA into buffer register D2.
(In Display Terminals employing the One-Step Transmit option, depression of
only the END key develops this signal.) With STX in D3 and DA in D2, the Display
Terminal is ready to transmit data to the CPU.
As soon as the cursor is located,
the first data character is shifted into buffer register Dl from the character entry
register.
Once the registers are filled, the cursor is released and again
permitted to circulate in the refresh memory loop.
With a 7-bit character held in buffer register D3, a start bit is generated
by the la-bit character forming network.
Data held in D3 is then serially shifted
at 1200 baud to both the parity check and generation circuit and to a transmitter
driver circuit on A14.
At the end of 8 bit-time s, a parity bit is generated by the
parity check and generation circuitry.
During the next bit-time, a stop bit is
placed on the line to complete the formation of the la-bit character.
To summarize the transmit mode, the flow of data is from the delay-line
memory into a portion of the character entry register.
From this point, serial
data is transferred through buffer registers Dl and D2 by the high-speed internal
timing into D3.
From buffer register D3, data is shifted at 1200 baud during the
proper bit-times (bits bi through b7) to the send data transmitter and then out to
the CPU I/O device over the transmitted data line.
Both before and after
actual data transfer, start, stop, and parity bits are generated to complete the
la-bit transmitted character.
4-16.2 Receive Mode
In the receive mode, the buffer registers are used to provide temporary
storage of data received from the CPU.
As each received character is held
in buffer registers Dl and D3, several parallel-connected decodes are employed
to examine the character coding.
When the Display Terminal is not actively transmitting data, digital
information on the received data line is permitted to enter buffer register Dl.
However, data received from the CPU is not gated to the remaining buffer
4-37
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