Raytheon DIDS-400 Series Technical Manual page 132

DIDS-402 -2AM13
If any character following DA is found to have an erroneous number of lis
a parity error code is jammed into Dl during the deci:mal counter parity count.
This code (0011010) is jammed into the register 'on-top-of' the erroneous charac-
ter by means of gate A56. 12. The code is transferred in the usual manner
through D2 and D3 and into the delay line. The code appears on the CRT screen
as a blank space in place of the erroneo·us character.
In the polling conversational mode, a 'II in the MSB of the address code
resets the STX flip-flop and inhibits the RE level. If the following character is
an ETX, ETX decode A 74.8 produces an output to enable one input to A 72.8
and subsequently Initialize Trans:mit when an ETX is found in the memory.
In the transtnit mode, Dl has an entirely different role. Since two forms
of operation are involved, depending upon the conversational mode, each for:m
is described separately. To assist in understanding the following text, alter-
nately refer to figures 4-28, 4-29, and 4-32.
In the polling conversational mode, Enter Header simultaneously performs
the following:
a. Jams STX into D3, DA into D2, and ETX into Dl, and sets
BB3, BB2, and BBI
b. Inhibits setting SDL until an ETX is detected in the refresh memory
loop (see figure 4-29)
c. Sets flip-flop A 78.11 to enable clearing BBI when an ETX is
detected in the refresh memory loop (see figure 4-24)
d. Enables setting T high after a delay of 16 :ms
After T goes high, the STX character in D3 is shifted out at the 1200-baud
transtnission rate. Simultaneously, the memory is accessed in search of an
ETX code. The specific operation of Dr depends upon whether or not an ETX
has been inserted into memory by the operator.
Assurn.ing that an ETX code is found in memory, BB 1 is cleared. This,
in turn, enables setting SDL as soon as the cursor is shifted into the character
entry register from the delay line. Note that it may easily take more than
16 ms to find both the ETX code and the cursor in memory. During this time,
STX and a portion of DA have been transtnitted to the CPU leaving D2 empty.
As soon as the cursor is found, SDL goes high to enable NAND-gate A50. 8.
Seven fast clock pulses are gated through A14. 6 to clock the character from
memory through NAND-gate A61. 11 and into Dl. This shift sets BBI which
in turn enables SGl2 since BB2 indicates a D2-empty status. SGl2 enables
NAND-gate A49. 8, and the character in Dl is shifted into D2. For each
successive character in :memory, the clock pulses applied to DI are alternately
enabled through NAND-gate A50. 8 (shift from delay line) or NAND-gate A49. 8
(shift from DI to D2). When ETX is finally shifted into Dl, decode A74. 8 is
enabled and, during 3CTS+l, an ERASE ETX pulse is produced. This pulse
sets a flip-flop (A9.1) on the display logic board which holds the delay-line
data-input line low for one character time, thus erasing the ETX character from
memory.
4-85