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DIDS-402 -2AM13
4-22.4.4.3 ETX Decode (see figure 4-36)
There are essentially two ETX decodes connected to D3.
One of the decodes,
A6.8, produces an output in either the transmit or the receive mode.
This
output is used to enable both the second ETX decode A18. 11, and the Enter EOT
wiring option circuitry (see paragraph 4-22.4. 3. 3). Although this option may be
enabled in either the transmit or receive mode, the optional operation has no
meaning in the receive mode (see below).
The second ETX decode, AI8.Il, is enabled only during RE due to AND-gate
AI9.6.
If an ETX control code is received without being preceded by an ESC code,
AND-gate A19.6 is enabled during 4(CTS+1).
This pulse is coupled through sec-
, ondary decode A18.11 and applied to the set input of cross-connected flip-flop
AI. II/AI. 8.
The flip-flop is set to enable 4{ CTS+1) to be gated through to pro-
duce an ETXD3 output.
Assuming for the moment that the Advance Line at
End of Receive option is not employed, ETXD3 has the sole function of resetting
the RE mode.
This is accomplished by simultaneously clearing the STX and
ADDR flip-flops and buffer registers D2 and D3.
When D3 is cleared, the
previously held ETX character is destroyed to prevent its entry into the delay-
line memory.
When the Advance Line at End of Receive option is used, a wire is connected
between terminals ET and NL.
Thus, when the ETXD3 pulse is developed by
4{CTS+I), two outputs are produced which result in erasing the line and advancing
the cursor to the first character position of the next line.
4-23 DISPLAY LOGIC BOARD Al3
The display logic board functions as a keyboard interface to permit entry
of 7-bit data characters from the keyboard.
The character entry and readout
register contained on this board enable visual characters on the CRT screen to
be displayed and refreshed.
Included on this board are various edit and cursor
control circuits which enable keyboard operators or CPU programs to edit and
format the screen presentation.
4-23. I
Character Entry Register
The character entry (CE) register, shown in figure 4-37, consists of eight
register flip-flops and a 'cursor-Iocated
1
flip-flop.
Data enters the character
entry register from three different sources: the delay line, the keyboard, or
buffer register D3.
In the transmit mode, data is extracted from memory by
coupling data from the CE register MSB flip-flop to buffer register Dl.
The
source of input data is dependent upon the operating status of the Display
Terminal at any particular moment as pointed out in the following text.
4-23. 1. I
Data from Delay Line
The CE register (as part of the refresh memory loop) accepts data
characters from the delay line, causes the character to be displayed on the
screen, and then returns the character to the delay line.
As stated previously,
the delay line is an internal storage device that provides a 16. 026-ms delay
of data between input and output.
Since the CE register is connected in series
4-96
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