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DIDS-402-2AM13
If an ETX code is not found in memory, BB 1 is not cleared and SDL is
therefore inhibited.
As soon as DA is shifted out of D2, the D2 empty status
enables setting SG12.
SG12, in turn, enables seven fast clock pulses through
NAND-gate A49.
B.
In
this manner, the ETX character held in Dl is shifted
to D2.
When ETX is finally shifted out of D3, the transmit mode is terminated
~y
the transmit time-out circuit.
In
the enquiry-response conversational mode, Enter Header jams STX
into D3 and DA into D2 and transmission begins one frame time later when
F.6.03 enables T to go high.
This results
in
shifting out the header characters
while the cursor bit is being searched for in memory.
When the cursor is
located. SDL goes high to permit shifting the character associated with the cursor
into Dl.
SG12 is then enabled by BB1 and
i3B2,
and a serial transfer from Dl to
D2 occurs.
Transmission continues in this manner until ETX is shifted into Dl.
When this occurs, the Erase ETX erases the code from memory.
When ETX
is
finally shifted out of D3. the transmit time-out circuit is enabled and trans-
mission is terminated •
. 4-22.4.3.2 Buffer Register D2.
Buffer register D2 (shown in figure 4-33)
consists of seven D-type flip·-flops which
sh~re
the common clock inputs from
inverter-driver
A3B. B.
In the receive mode, SG12 goes high when a D1-full, D2-empty status is
indicated by BB1 and BB2.
This enables seven
fast
clock pulses through NAND-
gate A49. B which shift the character out of D1 and into D2.
Since the RE steering
logic must be high in order to set BBl, STX and DA must be received by the
Display Terminal before a transfer of data from D1 into D2 is enabled.
Once
a character is shifted into D2, a D2-full and D3-empty status from BB2 and BB3
enables SG23. SG23 in turn enables NAND-gate A49. 6 and seven fast-clock
pulses are gated through
A3B. B
to shift the character from D2 to D3.
In the transmit mode, Initialize Transmit goes low to jam a NULL charac-
ter (0000000) into D2.
Up to 16 ms later, Enter Header jams a previously
determined device DA code into D2.
This address character may correspond
to anyone of 64 different DA'savailab1e for use by the system.
In any case,
the address code jammed into D2 normally corresponds to the address code
decoded by the DA decode connected to Dl.
When DA is jammed into D2, BB2 is set to indicate the D2 full status.
As soon as STX is shifted out of D3
(B.33
ms after T goes high), a BB2 and BB3
status enables SG23 to transfer the DA code from D2 to D3.
4-22.4.3.3 Buffer Register D3.
Buffer register D3 and its associated
circuits are shown in figures 4-34 and Raytheon Drawing No. 40B025.
The
register consists of seven D-type flip-flops which share common clock inputs
from inverter driver A14.
B.
In the receive mode, SG23 goes high when a D2 full, D3 empty status is
indicated by BB2 and BB3.
This enables NAND-gate A49. 6, and seven fast clock
pulses are applied to D3 to shift the character into the register.
BB3 is set as a
result of the D3 full condition and the next time the cursor appears in the charac-
4-B6
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