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DIDS-402-2AMl3
4-22.4. 1. 1 Busy-Bit One
Busy-bit one (BB
1)
is a
J -K
type flip-flop used to indicate a full or not full
condition for buffer register Dl (see figure 4-28).
The norm.al condition of BBl
is reset due to a low applied to the clear input following a transm.it or receive
sequence (ETXD3).
In the polling conversational m.ode, strapping term.inals PA and PB are
connected to provide a m.eans for setting BBI when Enter Header jam.s an ETX
character into buffer register DI.
As previously stated, ETX rem.ains in DI
until an ETX code is detected in m.em.ory.
When, or if, an ETX is located in
m.em.ory, BBI is cleared by ETX Found.
This perm.its the first m.essage
character to be shifted into Dl 'on-top-of' the ETX code.
BBI m.ay also be set by input levels applied through NOR-gate A29.
6.
In
the receive m.ode, BBI is set by 8AR and RE occurring in coincidence.
8AR is
one phase A pulse which occurs during the parity bit of each character received
after STX and DA.
In the transm.it m.ode, BBI is set when the cursor is found
in m.em.ory.
The cursor sets SDL (see paragraph4-22. 4. 2.3) which, in turn,
enables a character to be shifted out of m.em.ory and into buffer register Dl.
BBl is reset when SGl2 transfers the character from. DI to D2.
Note that
in the transm.it m.ode, BBl is reset when SDL goes low.
This occurs m.om.en-
tarily while the CRQ pulse is stepping the cursor to the right one character
position.
4-22.4.1.2 Busy-Bit Two
Busy-bit two (BB2) is used to indicate a full or not-full condition for
buffer register D2.
BB2 is reset following a transm.it or receive sequence by
ETXD3 and rem.ains reset until SGl2 enables a character transfer from. DI
to D2.
When the proper conditions exist to allow a transfer from. D2 to D3,
a level from. SG23 is com.bined with a SGl2 level to re set the busy bit.
In
term.s of data transfer, the character held in D2 is transferred to D3, and DI
does not contain a character for transfer to D2.
Thus, BB2 is reset because
D2 is em.pty after the transfer occurs.
Note ,however, that a sim.ultaneous
transfer can occur from. D2 to D3 and from. DI to D2 if buffer register DI
contains a character.
4 -22.4.
1.
3 Busy-Bit Three
Busy bit three (BB3) flip-flop provides a full or not full status indication
of buffer register D3.
Like the previously described busy bits, BB3 is reset
when an ETX character is decoded in D3.
A level from. SG23 sets BB3 when a
character is transferred from. D2 to D3.
In the receive m.ode, BB3 is reset
when SDL and RE appear in coincidence with SG23.
This indicates that the
character in D3 has been shifted into the delay line (SDL), but has not yet
been replaced by a character from. D2.
In the transm.it m.ode, BB3 is reset by
a phase
A
pulse which occurs during the parity bit of the character.
This indi-
cates that the last bit of the character has left the register and has entered the
transm.itted data interface circuit.
4-73
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