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DIDS-402-2AMI3
The character code is then serially shifted out of the entry register until,
after one character time (seven bit times), the following conditions are true:
(1)
the character entry register is cleared to form an IDLE code, (2) the charac-
ter readout register now contains an IDLE code (all l's), (3) the last bit of the
character code has just entered delay-line electronics, and (4) the CRT scan has
moved to the next character position on the screen.
In 16.026 ms, the character is returned to the character entry register,
and simultaneously the CRT scan is again at the line one character one position.
Thus, the character is again visually displayed and the screen presentation is
refreshed.
4-15.2.1 Delay-Line Electronics A9
The purpose of the delay-line electronics is to compensate for data attenu-
ation incurred in the delay line.
The circuit consists of two combination read-
write amplifiers which are connected in a series configuration between delay-line
sections.
Serial bit data from the character entry register is applied to the first
write amplifier and amplified to a level sufficient to drive the input transducer
of the first delay-line section.
The data passes through the delay line and
appears as an attenuated replica at the output transducer.
The data is then
amplified to its original level by the first read amplifier and applied to the second
write amplifier.
The proce ss is repeated for the second delay-line section and,
after encountering a total delay of 16.026 ms, the data is serially shifted into the
character entry register.
4-15.2.2 Delay Line A15
The purpose of the delay line is to provide an economic means of storing up
to 1040 data characters and 192 retrace characters in a compact area.
(Retrace
characters are actually not characters at all but merely blank spaces in the
delay line.) Data characters stored in the delay line are used to constantly
refre sh the CRT screen presentation.
In
addition, during the transmit sequence,
data character s are serially shifted out to the CPU upon the operator's or the
CPU's command.
The delay line consists of two separate sections which are series-connected
between the delay-line electronics read-write amplifiers.
Each section is
capable of storing 520 characters plus retrace, thus providing a total capability
of 1040 displayable character storage.
The delay-line sections (referred to as
the top and bottom sections) are electrically identical except for circuit placement
in the refresh memory loop.
As shown in figure 4-15, each delay-line section consists of the following
parts: an input transducer, rnagnetostrictive tapes, and transmission wires.
The input and output transducers are connected to the magnetostrictive tape s,
which are in turn welded to each end of the transmission wire.
4-33
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