Raytheon DIDS-400 Series Technical Manual page 93

DIDS-402-2AM13
The output delay logic consists of OR- gates AI. 8 and A20. 8. Similar to
the input display logic, the specific action taken on data as
it
leaves the delay
line and prepares to enter the character entry register is dependent upon the
operation initiated.
4-17.4 Insert and 12-Count Register
The insert and 12-count register is a 7-bit register used to assist in
performing the step-up and character-insert operations. Normally, the
register contains an IDLE character (all lIs) when it is not being employed by
the editing and cursor control logic.
In the insert operation, the insert and 12-count register is connected in
series with the refresh-memory loop, and the normal data path is interrupted.
This allows the IDLE character stored in the register to be inserted into the
memory loop as
a.
blank at the cursor position. The character previously asso-
ciated with the cursor, as well as all remaining characters on the line, are now
shifted into refresh memory via the insert and 12-count register. When the insert
operation is terminated, the register is removed from the circuit and the normal
data path is reestablished.
In the step-up operation, the insert and 12-count register functions as a
line counter. To accomplish a step-up, the cursor is moved from its character
position on a line to the same character position on the line above. The 12-count
register assists in this function by counting the number of active lines after the
initiation of the step-up operation. When the counter reaches the count of 12,
circuits elsewhere in the display logic place the cursor in the proper chara'cter
slot of the previous line. The 12-count output also resets the step-up flip-flop
and terminates the operation.
4-17.5 88-Count Register
The 88-count register is employed by the editing cursor control logic for
each operation requiring a count of the number of characters per line. The
functions requiring the .88-count register are: step-up, step-down, insert line,
and delete line. Normally, the counte r is held at a count corresponding to
binary zero. Once the counter is instructed to count, it begins counting in
binary until a count of 88 is decoded by AND-gate A36. 8. In the step-down
cursor control, it is necessary for the c.ounter to count to 88 only once. In the
remaining functions, however, the counter continues in the sequence 0-88-0-88,
etc., until the function is completed.
4-18 TIMING
All the display terminal timing circuits are located on timing and discrete
board A14. The internal timing consists of the various counters shown in
figure 4-18. A crystal-controlled master oscillator supplies a 'raw-clock
l
output of 2.4576 MHz, which is counted down by numerous dividers to arrive
at the internal timing signals. In addition, a free running multivibrator is used
to provide cycling frequencies of 6 Hz and 12 Hz for cycling selected display
te rminal function s.
4-42