Raytheon DIDS-400 Series Technical Manual page 126

DIDS-402-2AM13
(0 to 16 ITlS to locate the cur sor and 0 to 16 ITlS to perforITl
the cursor reset or erase ITlessage function). DC3 requires
up to 31 ITlS to perforITl (0 to 16 ITlS to locate the cursor and
15 ITlS to perforITl the step up function).
b. DCl, DC3, and CAN - These codes ITlust be followed by two
NULL characters.
Thus, if a control code (such as BS) is detected in D3, the function is
perforITled and point B goes high. Since BS also resets BB3, the next character
(a NULL code) is perITlitted to enter D3. As soon as NULL has been shifted into
, the register, A57.8 produces a low output which enables SDL. This, in turn,
resets BB3 and allows the next character (a NULL) to enter D3. This process
continues for still another NULL character until, after 33.32 ITlS, four charac-
ters have been received froITl the CPU. The fourth character (a text character)
is then in D3 and ITlay be acted upon in the norITlal ITlanner because Function
COITlplete has by then reset the CCC F
IF.
This is illustrated in figure 4-30.
DI
D2 D3 TiITle
Look for Cursor NULL NULL
BS
TO
NULL NULL
NULL
TO +8.33 ITlS
Cursor Found
PerforITl Function
TEXT NULL NULL
TO +16.66 ITlS
TEXT TEXT NULL
TO +24.99 ITlS
Function COITlplete TEXT
TEXT TEXT
TO +33.32 ITlS
OIDS 68-529
Figure 4- 30. Use of NULL Control Codes
4-22.4.2.3.5 TransITlit Mode - Text Character. In the transITlit ITlode,
the basic objective of the SDL circuitry is to enable data transfer froITl the
delay line to buffer register DI. Note that as soon as the request-to-send line
is raised (in either conversational ITlode), it is iITlpossible for RE to go high
until transITlission has ended. Thus D3 gate is disabled during transITlit and
data is not perITlitted to re-enter the delay line through NAND-gate A25.
6.
In the enquiry-response ITlode BBI, BB2~and BB3 are initially low due to
the ETXD3 pulse present at the end of the last transITlit or receive sequence.
Enter Header then jaITls STX and DA into D3 and D2, setting BB2 and BB3.
With BBI still low, NAND-gate A23.
6
is enabled when T goes high. As soon
as the cursor is found, SDL is set by 4(CTS+1) and clock pulses are applied to
Dl. These pulses shift the character associat with the cursor into buffer
register DI. During 1 (CTS+1), CRQ perforITls -a step-right function to auto-
ITlatically enable one input of AND-gate A56. 8. However, since it takes 8.33 ITlS
4-78