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DIDS-402-2AMI3
f.
Transfer contents of the delay line to buffer registers and from
buffer register D3 to the interface circuits
.s..
When ETX is detected in buffer register DI, begin transmit time-out
sequence
h.
When all buffer registers are empty, terminate transmit mode and
enter receive mode
The ETX code (entered into delay-line memory by the operator) circulates
through the refresh-memory loop.
Once per frame this character appears in the
character entry register and is decoded by NAND-gate A58. 8 on the Display Logic
Board.
An output pulse, ETXSR, is developed by NAND-gate A59. 8 as soon as
the character appears in the register.
On the Communications Control Board,
ETXSR is applied to NAND-gate A63. 8 in coincidence with the reset outputs of
A 78.3 and A62. 8.
When the XMIT key is depressed, the fourth input is satisfied
and an output is produced.
This low output is used to accomplish three functions:
(1) raise the request-to-send line, (2) clear the buffer registers (Initialize Trans-
mit), and (3) disable the receive (R) steering logic.
The request-to-send (RS) control level is amplified by interface circuits on
the timing and discrete board and coupled to a modem or similar device.
After
an established delay, a clear-to-send (CS) control signal is generated in reply
and applied to the input of AND-gate A54. 12.
The output of A54. 12 is applied to. inverter-driver A 77.8 in coincidence
with the re set output of flip-flop A62. 8.
The next F601 is gated through the
inverte r as Enter Header.
This pulse jams an STX character into buffer register
D3 and a predetermined address character into buffer register D2.
The Enter Header pulse also sets flip-flop A 78.11; the set output of the
flip-flop is applied in coincidence with
F~~3
to enable NAND-gate A69. 8.
The
lowgoing output sets flip-flop A 70. 11 to enable one input of NAND-gate A 70.8.
One phase time after A70.11 is set
(F~03-F~04),
flip-flop A78.11 is reset by an
FA~4
pulse.
The output of NAND-gate A 70.8 is used to produce the transmit (T) steering
logic level.
Again, because of optional wiring, the other inputs to A70. 8 may be
enabled only by clear-to- send, or clear-to- send and request-to-send appearing
. in coincidence.
In
any case, the output of A 70.8 is inverted and used through
the buffer register steering logic as a transmit steering level.
As shown in
figure 4-24, T and request-to-send remain high until the transmit time-out
flip-flop is set.
This circuit is described in the following text.
The purpose of the transmit time-out flip-flop is to reset the transmit and
receive enable circuitry to the receive (R) function.
Once the transmit steering
logic is enabled, data is extracted from the delay line each time the cursor bit
is located.
If at least one of the buffer registers is empty, the character code
is extracted from memory, shifted from DI through D3, and out to the interface
circuitry (see figure 4-24).
4-57
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