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DIDS-402.-2.AMI3
4-2.4. 11 Interface Circuits
The four interface circuits consist of transistorized amplifiers and level
shifters on the Ti:ming and Discrete Board.
The purpose of these circuits is to
level shift internal logic levels (0 and +5 vdc) to MIL-STD-188B levels of +6 and
--6
vdc.
These circuits also produce the drive levels necessary to co:mpensate
for the attenuation encountered by data or status levels coupled over the 50-foot
CPU I/O device interface cable.
The interface circuits are shown sche:matically
on Raytheon Drawing No. 407905.
4-25 DELAY-LINE ELECTRONICS A9 AND DELAY LINE Al5
The delay-line electronics board and the dual 8. 013-:ms delay line form a
part of the refresh :me:mory loop.
The delay line, which has a total storage
capacity of 1232 characte rs, provide s an econo:mical :means of storing data
intended for display.
Because of high delay-line attenuation, the read-write
a:mplifiers are used to a:mplify this data both before and after it is applied to
each delay-line section.
(Refer to Raytheon Drawing No. 389280.)
Serial data enters the delay-line electronics board at Idata-inl ter:minals
F and G.
True data is applied to ter:minal F, while the inverse
i~
applied to
te r:minal G.
I-C A4 contains four NAND-gate logic ele:ments which enable resynchronizing
the serial data with 012 clock pulses before applying it to the No. 1 delay-line
write a:mplifier.
The write a:mplifier, A5, consists of a push-pull a:mplifier which drives
opposite ends of the input transducer coil.
As the electrical i:mpulse s present
at the input coil are transfor:mer coupled into the output coil, a :mechanical
:movement is produced.
This :mechanical :move:ment (a twisting :motion) travels
down the magnetostrictive delay line and appears at the output transducer as an
attenuated output.
The output transducer is operated single-ended with the DATA signal
connected to ground through terminal A.
Attenuated data re-enters the delay-line
electronics at ter:minal B and is applied to the input (pin 1) of wide band power
a:mplifier AI.
The purpose of Al is to restore serial data to the sa:me a:mplitude
it possessed prior to entering the delay-line electronics board at ter:minal G. The
output of Al (pin 5) is coupled to the input of a D-type flip-flop in I-C A3.
The
fl..!.p-flops contained in A3 perform two functions: (1) data is resynchronized by
02 pulses to re-establish the original ti:me relationship of each bit; and (2) the
original DATA/DATA input is re-established by taking data fro:m both the set
and reset outputs of the flip-flop.
The preceding text has de scribed the flow of serial data fro:m its entrance
into the first write amplifier to a corresponding point at the entrance to the
second write amplifier.
The operation of the second delay-line section circuitry
is identical to that previously de scribed and therefore need not be repeated.
Exactly 8. 013 ms after data enters the second delay line at No. 2. delay-
line input, it appears at DATA OUT ter:minals Rand S.
Fro:m this point, the true
serial data at terminal S is coupled to the CE register via the output display logic.
4-153
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