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DIDS-402-2AMl3
When the INSRT key is depressed, A38.6 goes high to place a high at the
input to A30. 12.
Simultaneously, the low present at A38. 5 is coupled to the
88-count enable-reset circuit (see figure 4-48).
However, since the SHIFT key
is not depressed for the insert-character edit function, NAND-gate A22. 12 is
not enabled and the 88-count reset level at A29.11 remains high (see figure 4-51).
The high 88-Count Reset level is applied to one input of NAND-gate A23. 3.
When the cursor is located in the CE register, A30.l2 goes high to enable
NAND-gate AS
1.
3.
This permits shifting data into the extra insert register
before allowing the data to enter the delay line.
Simultaneously, A30.l3
interrupts the normal refresh-memory loop by placing a constant low at the
input to A4. 8.
The output of the insert register (which contains a previously stored Idle
character) is permitted to enter the refresh-memory loop through NAND-gate
ASO.l2.
Data flow through the newly established memory loop continues in this
manner, with the character codes being coupled from the' CE register to the
delay line via the insert register.
When the end-of-line (EOL) timing pulse
occurs (signifying the last character of the line), NAND-gate A23. 3 is enabled
to reset A30. 12.
When A30. 12 goes low, the insert register, which contains
the character previously displayed in the last character of line slot, is removed
from the loop.
Thus, a character-insert function inserts an IDLE character at
the cursor position and moves all other characters to the right by causing
them to appear in memory 13 I.I.s later.
The last character of the line is
destroyed when the insert register is removed from the loop.
4-23-3. 13 Insert Line Function
The insert-line edit function is similar in operation to the insert-character
function except that a SHIFT key depression causes insert character to be per-
formed 88 times.
To accomplish the insert-line function, the cursor must be
positioned to the first-character-of-line position before initiating the function
(see figures 4-51 and 4-48).
When the INSR T key is depressed in conjunction with a constant SHIFT key
depression (SHIFT LOCK), A38. S goes low to enable one input of NAND-gate
A22. 12 (88-count enable circuitry).
If the cursor is associated with the first
character of the line
(~),
AZ2.12 is enabled during 2CTS.
The low output
is used to latch A29. 3 high and thereby enable one input of NAND-gate A29. 16.
The 88-count circuit then begins counting up to 88.
Meanwhile, A30. 12 in
the insert circuit is set high when the cursor appears in the CE register.
This
enables an insert-character function to be performed.
At the end of the last horizontal line on the screen, an EOL pulse occurs in
coincidence with V DRIVE to enable A24. 12.
This resets A30. 12 to its normally
low status and disables the flow of data through the insert register.
Since A38. 6
is still high, a second insert-character function is enabled the next time the
cursor appears in the CE register.
The cursor clocks A30. 12 high to simul-
taneously inhibit A4. 8 and enable ASI. 3
4-133
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