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CTS OF
CHARAC
DIDS 68-561
80TH
TER
DIDS -402 -2AM 13
LINE COUNTER
(.;4)
9
12
9
12
A6
A6
All
All
8
13
8
13
6.
-
12
A13
IA17
-
-
8
J
A7 "-
I
V DRIVE
-
Figure 4-62.
Line Counter, Logic Diagram
NAND-gate A 7.8 is enabledafter CTS of the 80th character on line 13 clocks
the counter to line 14 (vertical retrace).
A V DRIVE pulse is developed which
simultaneously causes the vertical sweep to collapse and cuts off the video
amplifier.
The V DRIVE pulse remains low for 80 character times until the next
clock pulse toggles the counter and A17. 12 goes high.
When the V DRIVE pulse
returns to a high level at the 80th character of line 14, the horizontal drive goes
low to return the CRT scan to the left side of the screen.
During the 87th charac-
ter of line 14,
(~)
is gated through NAND-gate A13. 8 as
F(~)
to mark CTS of the
first character, first line position.
The line counter timing diagram is shown
in figure 4-63 and the overall timing diagram for the high- speed timing circuits
is shown in figure 4-64.
4-24.8 1200-Baud Circuitry
The purpose of the 1200-baud circuitry is to count down the CTS output of
the bit counter to develop a l200-baud clock for gating data to and from the
CPU 1/0 device.
The 1200-baud circuitry is formed by the gates and counters
illustrated in figure 4-65.
The l200-baud output pulses from inverter driver A24. 6 are controlled
by
the f/JA gate circuitry on the Communications Control Board A12.
When the
Display Terminal is not actively transmitting or receiving data, the l200-baud
counter and the 10-bit decimal counter are held reset by a i/JA GATE level present
at the output of A38. 6.
In the receive mode, the start bit of each incoming lO-bit character is used
to set A38. 6 high, thereby releasing the counter.
When the START bit is detected
by sensing a high-to-low transition of the received data line, AND-gate A4l. 6 is
enabled.
This produces a pulse out of A30. 8 which releases the 10-bit counter
(A24.6) and sets the f/JA gate output high (A38.6).
The counter then begins counting
CTS pulses which are coupled through AND-gate A35. 6.
4-145
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