Raytheon DIDS-400 Series Technical Manual page 127

DIDS-402 -2AM13
to transm.it the character held in D3, busy-bits BBl, BB2, and BB3 will all be
high and NAND-gate A23. 6 will be inhibited. This,in turn, inhibits setting SDL
and no further transfer from. m.em.ory can be accom.plished.
In 16 m.s, the cursor again appears at the input to AND-gate A56. 8. By
now, STX and DA should have been transm.itted and the first text character should
presently be in D3. The condition BBI and BB2 enables NAND-gate A23. 6, and
the second text character is shifted out of m.em.ory through Dl and into D2.
Since the cursor was again stepped right by CRQ, the condition BBI "and cursor
will enable the transfer of a second text character into Dl before the cursor is
released.
The transm.it operation continues in this m.anner until either the LF or
ETX control code is detected in Dl. Each tim.e the cursor enters the character
entry register, at least one, and usually two, characters are extracted from.
m.em.ory and shifted into DI.
When ETX is detected in Dl, the end-of-transm.ission is signified. The
com.bination of ETXDl, SDL, and T sets flip-flop Al 0.8 during 3(CTS+1). When
point A goes low, all further transfers from. the delay line are inhibited. When
BBl, BB2, and BB3 are all em.pty, the XMIT Tim.e Out pulse resets A50. 12 to
its quie scent state.
When LF is detected in Dl, a carriage return is indicated. Thus, all
characters of the line following LF are skipped and the read continues at the first
character position of the next line. The operation of the SDL circuitry under
these circum.stance s is determ.ined by flip-flop A13. 8. Point C is norm.ally
high due to 4CTS pulses which reset A13. 8 once per character. In the absence
of a clock pulse, point C rem.ains high, enabling one input to AND-gate A56. 8.
When LF is detected in Dl during transm.it, 3(CTS+1) is gated through the
LFDI decode to set A13. 8. This then inhibits SDL for one character tim.e (until
the next 4CTS) and assures that the tim.e hazard of extracting the character
following "LF does not occur. When LFis detected in
Dl~
an advance-line cursor
control operation is perform.ed (see paragraph 4-23.3.4). This m.oves the cursor
from. 1 to 88 characters to the right. When the cursor is again located in the
character entry register, transfers from. the delay line are again enabled. Thus,
the characters between LF and the new cursor position are not extracted from.
m.em.ory and are therefore not transm.itted.
In
the polling conver sational m.ode, the operation of the SDL circuitry is
basically unchanged once data extraction is initiated. From. previous discussions,
STX, DA, and ETX are jam.rn.ed into D3, D2, and Dl, respectively, by Enter
Header. This occurs as soon as a polling read directive is detected. As shown
in figure 4-29, Enter Header also sets AlO. 8 to force point A low. The delay
line is then exam.ined to determ.ine whether ETX code has been entered by the"
operator.
If an ETX is located, ETX found clears BBI and sim.ultaneously
resets A50. 12. The com.bination of point A high and BBI enables NAND-gate
A23.6 and SDL perm.its shifting the first text character into Dl 'on-top-of' the
previously entered ETX character.
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