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DIDS-402-2AMI3
4-22.4.2 Shift Gates
There are three shift-gate flip-flops directly associated with the transfer
of data through the buffer registers and to/from the delay-line memory.
SGl2
and SG23 are used to enable clock pulses to shift serial data through buffer
registers DI, D2, and D3.
SDL is used
in
both the transmit and receive mOde
to enable clock pulses to DI and D3.
A fourth flip-flop, D3 GATE, is employed
to enable data transfers to the delay line during receive and to inhibit transfers
to the delay line during transmit.
4-22.4.2. I Shift Gate One-to-Two (SGI2)
SGl2 has the sole function of enabling the application of clock pulses to
buffer registers DI and D2.
SGl2 is enabled when any of the following conditions
exist:
a.
Buffer register DI is full and D2 is empty
b.
Buffer register DI is full and D3 is empty
c.
Buffer register DI is full and D3 is full, but the character in D3 is
about to be shifted into the delay line
In
either the transmit or the receive mode, when DI contains a character
the remaining registers are examined for an empty status.
Note that the
condition D2-full and D3-empty results in a simultaneous transfer from D2 to
D3 and from DI to D2.
This is what occurs under the condition specified
in"
paragraph 4-22.4.2. 2b.
The condition stated in
(~
will have the same effect
since the character in D3 will enter the delay line at the same time the character
contained in D2 is shifted into D3.
4-22.4.2.2 Shift Gate Two-to- Three (SG23)
SG23 enables the application of clock pulses to buffer registers D2 and D3
when the following conditions exist:
a.
Buffer register D2 is full and D3 is empty
b.
Buffer register D2 is full and D3 is full, but the character contained
in D3 is about to be shifted into the delay line.
In
either the transmit or the receive mode, the condition D2 full enables
SG23 when D3 is empty.
If the D3 register is empty, as soon as the initial bits
of a character are shifted into D2, BB2 goe s high to enable a straight-through
transfer to D3.
The character, in effect, does not stop since both registers
are clocked simultaneously.
If the D3 register is full, however, SDL must be
enabled before the character held in D2 can be transferred.
The combination
SG23, RE, and SDL enables NAND-gate A23.12 to reset BB3 to produce BB3
output.
This level is then coupled to NAND-gate A40. 12 to enable SG23.
4-74
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