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T
SOL ..... - - I
3(CTS+1)
DIDS 68-528
LO
~
ETXOloT·SOL·3(CTS+1) - - - - . . . . . ,
LO=>ENTER HEADER
LO:::} XMIT TIME OUT
_-----01
LO:)CLEARBB1 .....
- - - - a
BB 1
_-----0.
BB2
_-----0
BB3
----..--Q-. . . .
CURSOR
TO A26.6
12
T_--I
(FROM CE
------1--.--1._--"
REGISTER)
LF01
'----.---' DECODE
HI~CCCF/F
®
A13
RE
BELL--.....,
NULL ......
- - - a
ENQ ...... -
.....
8
A33
DIDS-402 -2AM13
l(CTS+1)
12
b------~
CRQ
ENABLE 01
. . . - - - - - - - - - - -..... CLOCK
(T)
(3(CTS+1) )
....... _ _ _ _ _ _ _ _ _ _ .... ENABLE 03
CLOCK
(RE)
(3 (CTS+1)
1
03 GATE
I
11
1
p-__ ~1 0
Q~9~ ___ ~
CD
03 GATE
A33
8
4(CTS+1)
LO~
C R
Q
SOL 1 (CTS+l)
Q
8
~---+TO
CE
P--z-~L-"'"
REGISTER
ESCD3
_---41
LO~""--
BS, HT, VI, FF,
CR, DC1, DC3, CAN
IN 03
®
8
p-.........
RESET BB3
DATA
5
A13
LSB OF
BUFFER REG ISTER 03
Figure 4-29.
SDL, D3 Gate and Asso-
ciated Circuits, Logic
Diagram
4-71/4-72
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