Raytheon DIDS-400 Series Technical Manual page 164

DIDS-402 -2AM13
In the circuit quiescent state, Al3.5 is high and A8.l2 is low. When the
ERASE MSG key is depressed, A13.5 goes low to place a high at the J input of
A8.12. When the cursor is shifted into the CE register, A8.l2 goes high to
place a high at the input to the delay line. This, in turn, inserts an IDLE
character during the seven bits of each character. During the cursor slot, CTS
enables NAND-gate A16. 8 to inhibit placing a high at the cursor slot position.
The erase-m.essage function continues in this rn.anner for each character in
m.em.ory until
F(~}
occurs to signify the fram.e reset position (by now the entire
screen -from. the cursor position on has been erased).
F(~)
enables A16. II and
during 2CTS the function com.plete Q output goes high.
During the following
phase tim.e, 3(CTS+l) is gated through A18. 6 to return the circuit to its
quiescent state.
NOTE
The rem.aining edit or cursor control functions
require the assistance of auxiliary circuits in order
to accom.plish their functions. These circuits con-
sist of the 12-count and insert register and the
88-count circuit. These circuits are described
below so that the step-up, step-down, insert, and
delete functions m.ay be easily understood.
4-23.3.8 l2-Count and Insert Register
This circuit consists of eight flip-flops and associated gates shown in
figure 4-46. In the step-up function, the circuit acts as a counter and produces
a l2-count output. Since the counter is clocked by
~
pulses, the decoded output
corresponds to a count of 12 horizontal lines on the CRT screen. In the insert
function, the circuit acts as an 8-bit register. To insert a character, this
auxiliary register is connected in series with the refresh m.em.ory loop. As
such, it initially releases a stored IDLE code (a 'space ') which enters the delay
line at the cursor position. This 'space' perm.its entry of another character
at the cursor position. The register rem.ains in the circuit until the. function
is term.inated at the end of the line. Since the insert register then contains the
last character of the line, the character is rem.oved from. the loop and erased
from. the screen.
The operation of the l2-count and insert register is described in the
following text.
In the circuit quiescent state, a high is present at AS2.l2due to the absence
of coincident inputs to NAND-ga.tes AS!. 3 and A80. 3. Since the s!!p-up flip-flop
is considered to be inactive, NAND-gate A80. 8 is enabled during 02 to produce
phase 2 clock pulses for clocking the counter (register). Thus, at quiescence,
each flip-flop has a high present at the Q output.
For the step-up function, the
'all lis
I
condition corresponds to 0 count, while the insert function uses this
condition as a stored IDLE character.
4-120