Raytheon DIDS-400 Series Technical Manual page 191

DIDS-402-2AM13
Each l200-baud counter flip:-flop is connected in a divide-by-two arrange-
m.ent and after 32 CTS pulses have been counted, a '/JA pulse is deveJoped to gate
the first data bit into buffer register DI. Each tim.e a f/JA pulse is produced, B6
goes high and remains high for 32 CTS counts. The next f/JA pulse is produced
64 CTS pulses later when the l200-baud decodes are once again enabled. The
f/JA pulse s are offset in this m.anner in order to guarantee their occurrence during
the center of each bit tim.e of received data characters.
The 10-bit decim.al counter, which is clocked by f/JA output pulses, cycles
through 10 separate states which correspond to each bit of the received character.
After ten f/JA pulses have been counted, the 10-bit decimal counter toggles to a
STP state and NAND-gate A47. 12 is enabled by the B6 output at A37.ll. This
resets f/JA gate to a tnott condition and resets the l200-baud countdown by
resetting each counter and inhibiting AND-gate A35. 6. The counter is started
once more when the next START bit is detected on the received data line.
When the Display Terminal enters the transmit m.ode, Initialize XMIT
goes low to clear buffer registers D2 and D3 and set f/JA to a tnott condition. This
resets both the l200-baud and la-bit decim.al counters. When the first character
(STX) is jammed into D3, BB3 goes high to set the output of A38. 6 high and
thereby enable the counters.
After 32 CTS pulses have been counted, a '/JA pulse is developed to place
the start bit on the transm.itted data line. Sixty-four CTS pulses later, the first
data bit is shifted onto the transm.itted data line when the second f/JA pulse is
developed. Sim.ultaneously, the la-bit decimal counter is toggled to its next
state.
After ten '/JA pulses have been produced in this manner, the character code
in D3 has been shifted out to the CPU I/O device and the 10-bit counter has
returned to STP. During the time it takes for the 10-bit counter to toggle from
PAR to STP, anothe r character is shifted into D3. Once again, this produces a
BB3.T level to enable the l200-baud counter. The counter continues to operate in
this manner until the last character of the message has been transmitted. When
all three buffer registers empty, a '/J3 pulse is gated through as an end-of-transmi1
level to reset the f/JA gate flip-flop to its quiescent state (0A GATE). This level
resets the l200-baud and la-bit decim.al counters to their quiescent counts of all
01S and STP, respectively.
4-24.9 la-Bit Decim.al Counter
The purpose of the la-bit decimal counter is to produce outputs in coinci-
dence with the START, PARITY and STOP bits of each transmitted or received
data character. The la-bit decim.al counter is shown in figure 4-66.
Norm.ally, the la-bit decim.al counter is jammed to an STP output by
-:J0-,A,.....--:G=A~T=-E=.
As stated in paragraph 4-24.8, specific conditions are detected
during transm.it or receive which release the counter and allow it to cycle through
the 10 states shown in figure 4-67.
4-149